1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cirrus Logic CS35L56 smart amp 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/acpi.h> 9 #include <linux/completion.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/math.h> 16 #include <linux/module.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <linux/soundwire/sdw.h> 23 #include <linux/types.h> 24 #include <linux/workqueue.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/tlv.h> 30 31 #include "wm_adsp.h" 32 #include "cs35l56.h" 33 34 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 35 struct snd_kcontrol *kcontrol, int event); 36 37 static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56) 38 { 39 /* Wait for patching to complete */ 40 flush_work(&cs35l56->dsp_work); 41 } 42 43 static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol, 44 struct snd_ctl_elem_value *ucontrol) 45 { 46 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 47 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 48 49 cs35l56_wait_dsp_ready(cs35l56); 50 return snd_soc_get_volsw(kcontrol, ucontrol); 51 } 52 53 static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol, 54 struct snd_ctl_elem_value *ucontrol) 55 { 56 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 57 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 58 59 cs35l56_wait_dsp_ready(cs35l56); 60 return snd_soc_put_volsw(kcontrol, ucontrol); 61 } 62 63 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0); 64 65 static const struct snd_kcontrol_new cs35l56_controls[] = { 66 SOC_SINGLE_EXT("Speaker Switch", 67 CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1, 68 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 69 SOC_SINGLE_S_EXT_TLV("Speaker Volume", 70 CS35L56_MAIN_RENDER_USER_VOLUME, 71 6, -400, 400, 9, 0, 72 cs35l56_dspwait_get_volsw, 73 cs35l56_dspwait_put_volsw, 74 vol_tlv), 75 SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER, 76 0, 255, 0, 77 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 78 }; 79 80 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum, 81 CS35L56_ASP1TX1_INPUT, 82 0, CS35L56_ASP_TXn_SRC_MASK, 83 cs35l56_tx_input_texts, 84 cs35l56_tx_input_values); 85 86 static const struct snd_kcontrol_new asp1_tx1_mux = 87 SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum); 88 89 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum, 90 CS35L56_ASP1TX2_INPUT, 91 0, CS35L56_ASP_TXn_SRC_MASK, 92 cs35l56_tx_input_texts, 93 cs35l56_tx_input_values); 94 95 static const struct snd_kcontrol_new asp1_tx2_mux = 96 SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum); 97 98 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum, 99 CS35L56_ASP1TX3_INPUT, 100 0, CS35L56_ASP_TXn_SRC_MASK, 101 cs35l56_tx_input_texts, 102 cs35l56_tx_input_values); 103 104 static const struct snd_kcontrol_new asp1_tx3_mux = 105 SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum); 106 107 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum, 108 CS35L56_ASP1TX4_INPUT, 109 0, CS35L56_ASP_TXn_SRC_MASK, 110 cs35l56_tx_input_texts, 111 cs35l56_tx_input_values); 112 113 static const struct snd_kcontrol_new asp1_tx4_mux = 114 SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum); 115 116 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum, 117 CS35L56_SWIRE_DP3_CH1_INPUT, 118 0, CS35L56_SWIRETXn_SRC_MASK, 119 cs35l56_tx_input_texts, 120 cs35l56_tx_input_values); 121 122 static const struct snd_kcontrol_new sdw1_tx1_mux = 123 SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum); 124 125 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum, 126 CS35L56_SWIRE_DP3_CH2_INPUT, 127 0, CS35L56_SWIRETXn_SRC_MASK, 128 cs35l56_tx_input_texts, 129 cs35l56_tx_input_values); 130 131 static const struct snd_kcontrol_new sdw1_tx2_mux = 132 SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum); 133 134 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum, 135 CS35L56_SWIRE_DP3_CH3_INPUT, 136 0, CS35L56_SWIRETXn_SRC_MASK, 137 cs35l56_tx_input_texts, 138 cs35l56_tx_input_values); 139 140 static const struct snd_kcontrol_new sdw1_tx3_mux = 141 SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum); 142 143 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum, 144 CS35L56_SWIRE_DP3_CH4_INPUT, 145 0, CS35L56_SWIRETXn_SRC_MASK, 146 cs35l56_tx_input_texts, 147 cs35l56_tx_input_values); 148 149 static const struct snd_kcontrol_new sdw1_tx4_mux = 150 SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum); 151 152 static int cs35l56_play_event(struct snd_soc_dapm_widget *w, 153 struct snd_kcontrol *kcontrol, int event) 154 { 155 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 156 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 157 unsigned int val; 158 int ret; 159 160 dev_dbg(cs35l56->base.dev, "play: %d\n", event); 161 162 switch (event) { 163 case SND_SOC_DAPM_PRE_PMU: 164 /* Don't wait for ACK, we check in POST_PMU that it completed */ 165 return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 166 CS35L56_MBOX_CMD_AUDIO_PLAY); 167 case SND_SOC_DAPM_POST_PMU: 168 /* Wait for firmware to enter PS0 power state */ 169 ret = regmap_read_poll_timeout(cs35l56->base.regmap, 170 CS35L56_TRANSDUCER_ACTUAL_PS, 171 val, (val == CS35L56_PS0), 172 CS35L56_PS0_POLL_US, 173 CS35L56_PS0_TIMEOUT_US); 174 if (ret) 175 dev_err(cs35l56->base.dev, "PS0 wait failed: %d\n", ret); 176 return ret; 177 case SND_SOC_DAPM_POST_PMD: 178 return cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PAUSE); 179 default: 180 return 0; 181 } 182 } 183 184 static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = { 185 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0), 186 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0), 187 188 SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event, 189 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 190 191 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0), 192 SND_SOC_DAPM_OUTPUT("SPK"), 193 194 SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event, 195 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 196 197 SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1, 198 CS35L56_ASP_RX1_EN_SHIFT, 0), 199 SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1, 200 CS35L56_ASP_RX2_EN_SHIFT, 0), 201 SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1, 202 CS35L56_ASP_TX1_EN_SHIFT, 0), 203 SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1, 204 CS35L56_ASP_TX2_EN_SHIFT, 0), 205 SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1, 206 CS35L56_ASP_TX3_EN_SHIFT, 0), 207 SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1, 208 CS35L56_ASP_TX4_EN_SHIFT, 0), 209 210 SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux), 211 SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux), 212 SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux), 213 SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux), 214 215 SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux), 216 SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux), 217 SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux), 218 SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux), 219 220 SND_SOC_DAPM_SIGGEN("VMON ADC"), 221 SND_SOC_DAPM_SIGGEN("IMON ADC"), 222 SND_SOC_DAPM_SIGGEN("ERRVOL ADC"), 223 SND_SOC_DAPM_SIGGEN("CLASSH ADC"), 224 SND_SOC_DAPM_SIGGEN("VDDBMON ADC"), 225 SND_SOC_DAPM_SIGGEN("VBSTMON ADC"), 226 SND_SOC_DAPM_SIGGEN("TEMPMON ADC"), 227 }; 228 229 #define CS35L56_SRC_ROUTE(name) \ 230 { name" Source", "ASP1RX1", "ASP1RX1" }, \ 231 { name" Source", "ASP1RX2", "ASP1RX2" }, \ 232 { name" Source", "VMON", "VMON ADC" }, \ 233 { name" Source", "IMON", "IMON ADC" }, \ 234 { name" Source", "ERRVOL", "ERRVOL ADC" }, \ 235 { name" Source", "CLASSH", "CLASSH ADC" }, \ 236 { name" Source", "VDDBMON", "VDDBMON ADC" }, \ 237 { name" Source", "VBSTMON", "VBSTMON ADC" }, \ 238 { name" Source", "DSP1TX1", "DSP1" }, \ 239 { name" Source", "DSP1TX2", "DSP1" }, \ 240 { name" Source", "DSP1TX3", "DSP1" }, \ 241 { name" Source", "DSP1TX4", "DSP1" }, \ 242 { name" Source", "DSP1TX5", "DSP1" }, \ 243 { name" Source", "DSP1TX6", "DSP1" }, \ 244 { name" Source", "DSP1TX7", "DSP1" }, \ 245 { name" Source", "DSP1TX8", "DSP1" }, \ 246 { name" Source", "TEMPMON", "TEMPMON ADC" }, \ 247 { name" Source", "INTERPOLATOR", "AMP" }, \ 248 { name" Source", "SDW1RX1", "SDW1 Playback" }, \ 249 { name" Source", "SDW1RX2", "SDW1 Playback" }, 250 251 static const struct snd_soc_dapm_route cs35l56_audio_map[] = { 252 { "AMP", NULL, "VDD_B" }, 253 { "AMP", NULL, "VDD_AMP" }, 254 255 { "ASP1 Playback", NULL, "PLAY" }, 256 { "SDW1 Playback", NULL, "PLAY" }, 257 258 { "ASP1RX1", NULL, "ASP1 Playback" }, 259 { "ASP1RX2", NULL, "ASP1 Playback" }, 260 { "DSP1", NULL, "ASP1RX1" }, 261 { "DSP1", NULL, "ASP1RX2" }, 262 { "DSP1", NULL, "SDW1 Playback" }, 263 { "AMP", NULL, "DSP1" }, 264 { "SPK", NULL, "AMP" }, 265 266 CS35L56_SRC_ROUTE("ASP1 TX1") 267 CS35L56_SRC_ROUTE("ASP1 TX2") 268 CS35L56_SRC_ROUTE("ASP1 TX3") 269 CS35L56_SRC_ROUTE("ASP1 TX4") 270 271 { "ASP1TX1", NULL, "ASP1 TX1 Source" }, 272 { "ASP1TX2", NULL, "ASP1 TX2 Source" }, 273 { "ASP1TX3", NULL, "ASP1 TX3 Source" }, 274 { "ASP1TX4", NULL, "ASP1 TX4 Source" }, 275 { "ASP1 Capture", NULL, "ASP1TX1" }, 276 { "ASP1 Capture", NULL, "ASP1TX2" }, 277 { "ASP1 Capture", NULL, "ASP1TX3" }, 278 { "ASP1 Capture", NULL, "ASP1TX4" }, 279 280 CS35L56_SRC_ROUTE("SDW1 TX1") 281 CS35L56_SRC_ROUTE("SDW1 TX2") 282 CS35L56_SRC_ROUTE("SDW1 TX3") 283 CS35L56_SRC_ROUTE("SDW1 TX4") 284 { "SDW1 Capture", NULL, "SDW1 TX1 Source" }, 285 { "SDW1 Capture", NULL, "SDW1 TX2 Source" }, 286 { "SDW1 Capture", NULL, "SDW1 TX3 Source" }, 287 { "SDW1 Capture", NULL, "SDW1 TX4 Source" }, 288 }; 289 290 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 291 struct snd_kcontrol *kcontrol, int event) 292 { 293 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 294 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 295 296 dev_dbg(cs35l56->base.dev, "%s: %d\n", __func__, event); 297 298 return wm_adsp_event(w, kcontrol, event); 299 } 300 301 static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 302 { 303 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component); 304 unsigned int val; 305 306 dev_dbg(cs35l56->base.dev, "%s: %#x\n", __func__, fmt); 307 308 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 309 case SND_SOC_DAIFMT_CBC_CFC: 310 break; 311 default: 312 dev_err(cs35l56->base.dev, "Unsupported clock source mode\n"); 313 return -EINVAL; 314 } 315 316 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 317 case SND_SOC_DAIFMT_DSP_A: 318 val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT; 319 cs35l56->tdm_mode = true; 320 break; 321 case SND_SOC_DAIFMT_I2S: 322 val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT; 323 cs35l56->tdm_mode = false; 324 break; 325 default: 326 dev_err(cs35l56->base.dev, "Unsupported DAI format\n"); 327 return -EINVAL; 328 } 329 330 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 331 case SND_SOC_DAIFMT_NB_IF: 332 val |= CS35L56_ASP_FSYNC_INV_MASK; 333 break; 334 case SND_SOC_DAIFMT_IB_NF: 335 val |= CS35L56_ASP_BCLK_INV_MASK; 336 break; 337 case SND_SOC_DAIFMT_IB_IF: 338 val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK; 339 break; 340 case SND_SOC_DAIFMT_NB_NF: 341 break; 342 default: 343 dev_err(cs35l56->base.dev, "Invalid clock invert\n"); 344 return -EINVAL; 345 } 346 347 regmap_update_bits(cs35l56->base.regmap, 348 CS35L56_ASP1_CONTROL2, 349 CS35L56_ASP_FMT_MASK | 350 CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK, 351 val); 352 353 /* Hi-Z DOUT in unused slots and when all TX are disabled */ 354 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3, 355 CS35L56_ASP1_DOUT_HIZ_CTRL_MASK, 356 CS35L56_ASP_UNUSED_HIZ_OFF_HIZ); 357 358 return 0; 359 } 360 361 static unsigned int cs35l56_make_tdm_config_word(unsigned int reg_val, unsigned long mask) 362 { 363 unsigned int channel_shift; 364 int bit_num; 365 366 /* Enable consecutive TX1..TXn for each of the slots set in mask */ 367 channel_shift = 0; 368 for_each_set_bit(bit_num, &mask, 32) { 369 reg_val &= ~(0x3f << channel_shift); 370 reg_val |= bit_num << channel_shift; 371 channel_shift += 8; 372 } 373 374 return reg_val; 375 } 376 377 static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 378 unsigned int rx_mask, int slots, int slot_width) 379 { 380 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 381 382 if ((slots == 0) || (slot_width == 0)) { 383 dev_dbg(cs35l56->base.dev, "tdm config cleared\n"); 384 cs35l56->asp_slot_width = 0; 385 cs35l56->asp_slot_count = 0; 386 return 0; 387 } 388 389 if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) { 390 dev_err(cs35l56->base.dev, "tdm invalid slot width %d\n", slot_width); 391 return -EINVAL; 392 } 393 394 /* More than 32 slots would give an unsupportable BCLK frequency */ 395 if (slots > 32) { 396 dev_err(cs35l56->base.dev, "tdm invalid slot count %d\n", slots); 397 return -EINVAL; 398 } 399 400 cs35l56->asp_slot_width = (u8)slot_width; 401 cs35l56->asp_slot_count = (u8)slots; 402 403 // Note: rx/tx is from point of view of the CPU end 404 if (tx_mask == 0) 405 tx_mask = 0x3; // ASPRX1/RX2 in slots 0 and 1 406 407 if (rx_mask == 0) 408 rx_mask = 0xf; // ASPTX1..TX4 in slots 0..3 409 410 /* Default unused slots to 63 */ 411 regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL1, 412 cs35l56_make_tdm_config_word(0x3f3f3f3f, rx_mask)); 413 regmap_write(cs35l56->base.regmap, CS35L56_ASP1_FRAME_CONTROL5, 414 cs35l56_make_tdm_config_word(0x3f3f3f, tx_mask)); 415 416 dev_dbg(cs35l56->base.dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n", 417 cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask); 418 419 return 0; 420 } 421 422 static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream, 423 struct snd_pcm_hw_params *params, 424 struct snd_soc_dai *dai) 425 { 426 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 427 unsigned int rate = params_rate(params); 428 u8 asp_width, asp_wl; 429 430 asp_wl = params_width(params); 431 if (cs35l56->asp_slot_width) 432 asp_width = cs35l56->asp_slot_width; 433 else 434 asp_width = asp_wl; 435 436 dev_dbg(cs35l56->base.dev, "%s: wl=%d, width=%d, rate=%d", 437 __func__, asp_wl, asp_width, rate); 438 439 if (!cs35l56->sysclk_set) { 440 unsigned int slots = cs35l56->asp_slot_count; 441 unsigned int bclk_freq; 442 int freq_id; 443 444 if (slots == 0) { 445 slots = params_channels(params); 446 447 /* I2S always has an even number of slots */ 448 if (!cs35l56->tdm_mode) 449 slots = round_up(slots, 2); 450 } 451 452 bclk_freq = asp_width * slots * rate; 453 freq_id = cs35l56_get_bclk_freq_id(bclk_freq); 454 if (freq_id < 0) { 455 dev_err(cs35l56->base.dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq); 456 return -EINVAL; 457 } 458 459 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1, 460 CS35L56_ASP_BCLK_FREQ_MASK, 461 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 462 } 463 464 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 465 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2, 466 CS35L56_ASP_RX_WIDTH_MASK, asp_width << 467 CS35L56_ASP_RX_WIDTH_SHIFT); 468 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL5, 469 CS35L56_ASP_RX_WL_MASK, asp_wl); 470 } else { 471 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2, 472 CS35L56_ASP_TX_WIDTH_MASK, asp_width << 473 CS35L56_ASP_TX_WIDTH_SHIFT); 474 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL1, 475 CS35L56_ASP_TX_WL_MASK, asp_wl); 476 } 477 478 return 0; 479 } 480 481 static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai, 482 int clk_id, unsigned int freq, int dir) 483 { 484 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 485 int freq_id; 486 487 if (freq == 0) { 488 cs35l56->sysclk_set = false; 489 return 0; 490 } 491 492 freq_id = cs35l56_get_bclk_freq_id(freq); 493 if (freq_id < 0) 494 return freq_id; 495 496 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1, 497 CS35L56_ASP_BCLK_FREQ_MASK, 498 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 499 cs35l56->sysclk_set = true; 500 501 return 0; 502 } 503 504 static const struct snd_soc_dai_ops cs35l56_ops = { 505 .set_fmt = cs35l56_asp_dai_set_fmt, 506 .set_tdm_slot = cs35l56_asp_dai_set_tdm_slot, 507 .hw_params = cs35l56_asp_dai_hw_params, 508 .set_sysclk = cs35l56_asp_dai_set_sysclk, 509 }; 510 511 static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream, 512 struct snd_soc_dai *dai) 513 { 514 snd_soc_dai_set_dma_data(dai, substream, NULL); 515 } 516 517 static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 518 unsigned int rx_mask, int slots, int slot_width) 519 { 520 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 521 522 /* rx/tx are from point of view of the CPU end so opposite to our rx/tx */ 523 cs35l56->rx_mask = tx_mask; 524 cs35l56->tx_mask = rx_mask; 525 526 return 0; 527 } 528 529 static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream, 530 struct snd_pcm_hw_params *params, 531 struct snd_soc_dai *dai) 532 { 533 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 534 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 535 struct sdw_stream_config sconfig; 536 struct sdw_port_config pconfig; 537 int ret; 538 539 dev_dbg(cs35l56->base.dev, "%s: rate %d\n", __func__, params_rate(params)); 540 541 if (!cs35l56->base.init_done) 542 return -ENODEV; 543 544 if (!sdw_stream) 545 return -EINVAL; 546 547 memset(&sconfig, 0, sizeof(sconfig)); 548 memset(&pconfig, 0, sizeof(pconfig)); 549 550 sconfig.frame_rate = params_rate(params); 551 sconfig.bps = snd_pcm_format_width(params_format(params)); 552 553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 554 sconfig.direction = SDW_DATA_DIR_RX; 555 pconfig.num = CS35L56_SDW1_PLAYBACK_PORT; 556 pconfig.ch_mask = cs35l56->rx_mask; 557 } else { 558 sconfig.direction = SDW_DATA_DIR_TX; 559 pconfig.num = CS35L56_SDW1_CAPTURE_PORT; 560 pconfig.ch_mask = cs35l56->tx_mask; 561 } 562 563 if (pconfig.ch_mask == 0) { 564 sconfig.ch_count = params_channels(params); 565 pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0); 566 } else { 567 sconfig.ch_count = hweight32(pconfig.ch_mask); 568 } 569 570 ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig, 571 1, sdw_stream); 572 if (ret) { 573 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 574 return ret; 575 } 576 577 return 0; 578 } 579 580 static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream, 581 struct snd_soc_dai *dai) 582 { 583 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 584 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 585 586 if (!cs35l56->sdw_peripheral) 587 return -EINVAL; 588 589 sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream); 590 591 return 0; 592 } 593 594 static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai, 595 void *sdw_stream, int direction) 596 { 597 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 598 599 return 0; 600 } 601 602 static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = { 603 .set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot, 604 .shutdown = cs35l56_sdw_dai_shutdown, 605 .hw_params = cs35l56_sdw_dai_hw_params, 606 .hw_free = cs35l56_sdw_dai_hw_free, 607 .set_stream = cs35l56_sdw_dai_set_stream, 608 }; 609 610 static struct snd_soc_dai_driver cs35l56_dai[] = { 611 { 612 .name = "cs35l56-asp1", 613 .id = 0, 614 .playback = { 615 .stream_name = "ASP1 Playback", 616 .channels_min = 1, 617 .channels_max = 2, 618 .rates = CS35L56_RATES, 619 .formats = CS35L56_RX_FORMATS, 620 }, 621 .capture = { 622 .stream_name = "ASP1 Capture", 623 .channels_min = 1, 624 .channels_max = 4, 625 .rates = CS35L56_RATES, 626 .formats = CS35L56_TX_FORMATS, 627 }, 628 .ops = &cs35l56_ops, 629 .symmetric_rate = 1, 630 .symmetric_sample_bits = 1, 631 }, 632 { 633 .name = "cs35l56-sdw1", 634 .id = 1, 635 .playback = { 636 .stream_name = "SDW1 Playback", 637 .channels_min = 1, 638 .channels_max = 2, 639 .rates = CS35L56_RATES, 640 .formats = CS35L56_RX_FORMATS, 641 }, 642 .capture = { 643 .stream_name = "SDW1 Capture", 644 .channels_min = 1, 645 .channels_max = 4, 646 .rates = CS35L56_RATES, 647 .formats = CS35L56_TX_FORMATS, 648 }, 649 .symmetric_rate = 1, 650 .ops = &cs35l56_sdw_dai_ops, 651 } 652 }; 653 654 static void cs35l56_secure_patch(struct cs35l56_private *cs35l56) 655 { 656 int ret; 657 658 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 659 ret = wm_adsp_power_up(&cs35l56->dsp); 660 if (ret) 661 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 662 else 663 cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_REINIT); 664 } 665 666 static void cs35l56_patch(struct cs35l56_private *cs35l56) 667 { 668 int ret; 669 670 /* 671 * Disable SoundWire interrupts to prevent race with IRQ work. 672 * Setting sdw_irq_no_unmask prevents the handler re-enabling 673 * the SoundWire interrupt. 674 */ 675 if (cs35l56->sdw_peripheral) { 676 cs35l56->sdw_irq_no_unmask = true; 677 flush_work(&cs35l56->sdw_irq_work); 678 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0); 679 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1); 680 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF); 681 flush_work(&cs35l56->sdw_irq_work); 682 } 683 684 ret = cs35l56_firmware_shutdown(&cs35l56->base); 685 if (ret) 686 goto err; 687 688 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 689 ret = wm_adsp_power_up(&cs35l56->dsp); 690 if (ret) { 691 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 692 goto err; 693 } 694 695 mutex_lock(&cs35l56->base.irq_lock); 696 697 init_completion(&cs35l56->init_completion); 698 699 cs35l56->soft_resetting = true; 700 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral); 701 702 if (cs35l56->sdw_peripheral) { 703 /* 704 * The system-reset causes the CS35L56 to detach from the bus. 705 * Wait for the manager to re-enumerate the CS35L56 and 706 * cs35l56_init() to run again. 707 */ 708 if (!wait_for_completion_timeout(&cs35l56->init_completion, 709 msecs_to_jiffies(5000))) { 710 dev_err(cs35l56->base.dev, "%s: init_completion timed out (SDW)\n", 711 __func__); 712 goto err_unlock; 713 } 714 } else if (cs35l56_init(cs35l56)) { 715 goto err_unlock; 716 } 717 718 regmap_clear_bits(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS, 719 CS35L56_FIRMWARE_MISSING); 720 cs35l56->base.fw_patched = true; 721 722 err_unlock: 723 mutex_unlock(&cs35l56->base.irq_lock); 724 err: 725 /* Re-enable SoundWire interrupts */ 726 if (cs35l56->sdw_peripheral) { 727 cs35l56->sdw_irq_no_unmask = false; 728 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 729 CS35L56_SDW_INT_MASK_CODEC_IRQ); 730 } 731 } 732 733 static void cs35l56_dsp_work(struct work_struct *work) 734 { 735 struct cs35l56_private *cs35l56 = container_of(work, 736 struct cs35l56_private, 737 dsp_work); 738 739 if (!cs35l56->base.init_done) 740 return; 741 742 pm_runtime_get_sync(cs35l56->base.dev); 743 744 /* 745 * When the device is running in secure mode the firmware files can 746 * only contain insecure tunings and therefore we do not need to 747 * shutdown the firmware to apply them and can use the lower cost 748 * reinit sequence instead. 749 */ 750 if (cs35l56->base.secured) 751 cs35l56_secure_patch(cs35l56); 752 else 753 cs35l56_patch(cs35l56); 754 755 pm_runtime_mark_last_busy(cs35l56->base.dev); 756 pm_runtime_put_autosuspend(cs35l56->base.dev); 757 } 758 759 static int cs35l56_component_probe(struct snd_soc_component *component) 760 { 761 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 762 struct dentry *debugfs_root = component->debugfs_root; 763 764 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values)); 765 766 if (!wait_for_completion_timeout(&cs35l56->init_completion, 767 msecs_to_jiffies(5000))) { 768 dev_err(cs35l56->base.dev, "%s: init_completion timed out\n", __func__); 769 return -ENODEV; 770 } 771 772 cs35l56->component = component; 773 wm_adsp2_component_probe(&cs35l56->dsp, component); 774 775 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->base.init_done); 776 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->base.can_hibernate); 777 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->base.fw_patched); 778 779 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 780 781 return 0; 782 } 783 784 static void cs35l56_component_remove(struct snd_soc_component *component) 785 { 786 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 787 788 cancel_work_sync(&cs35l56->dsp_work); 789 } 790 791 static int cs35l56_set_bias_level(struct snd_soc_component *component, 792 enum snd_soc_bias_level level) 793 { 794 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 795 796 switch (level) { 797 case SND_SOC_BIAS_STANDBY: 798 /* 799 * Wait for patching to complete when transitioning from 800 * BIAS_OFF to BIAS_STANDBY 801 */ 802 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 803 cs35l56_wait_dsp_ready(cs35l56); 804 805 break; 806 default: 807 break; 808 } 809 810 return 0; 811 } 812 813 static const struct snd_soc_component_driver soc_component_dev_cs35l56 = { 814 .probe = cs35l56_component_probe, 815 .remove = cs35l56_component_remove, 816 817 .dapm_widgets = cs35l56_dapm_widgets, 818 .num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets), 819 .dapm_routes = cs35l56_audio_map, 820 .num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map), 821 .controls = cs35l56_controls, 822 .num_controls = ARRAY_SIZE(cs35l56_controls), 823 824 .set_bias_level = cs35l56_set_bias_level, 825 826 .suspend_bias_off = 1, /* see cs35l56_system_resume() */ 827 }; 828 829 static int __maybe_unused cs35l56_runtime_suspend_i2c_spi(struct device *dev) 830 { 831 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 832 833 return cs35l56_runtime_suspend_common(&cs35l56->base); 834 } 835 836 static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev) 837 { 838 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 839 840 return cs35l56_runtime_resume_common(&cs35l56->base, false); 841 } 842 843 int cs35l56_system_suspend(struct device *dev) 844 { 845 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 846 847 dev_dbg(dev, "system_suspend\n"); 848 849 if (cs35l56->component) 850 flush_work(&cs35l56->dsp_work); 851 852 /* 853 * The interrupt line is normally shared, but after we start suspending 854 * we can't check if our device is the source of an interrupt, and can't 855 * clear it. Prevent this race by temporarily disabling the parent irq 856 * until we reach _no_irq. 857 */ 858 if (cs35l56->base.irq) 859 disable_irq(cs35l56->base.irq); 860 861 return pm_runtime_force_suspend(dev); 862 } 863 EXPORT_SYMBOL_GPL(cs35l56_system_suspend); 864 865 int cs35l56_system_suspend_late(struct device *dev) 866 { 867 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 868 869 dev_dbg(dev, "system_suspend_late\n"); 870 871 /* 872 * Assert RESET before removing supplies. 873 * RESET is usually shared by all amps so it must not be asserted until 874 * all driver instances have done their suspend() stage. 875 */ 876 if (cs35l56->base.reset_gpio) { 877 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 878 cs35l56_wait_min_reset_pulse(); 879 } 880 881 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 882 883 return 0; 884 } 885 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late); 886 887 int cs35l56_system_suspend_no_irq(struct device *dev) 888 { 889 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 890 891 dev_dbg(dev, "system_suspend_no_irq\n"); 892 893 /* Handlers are now disabled so the parent IRQ can safely be re-enabled. */ 894 if (cs35l56->base.irq) 895 enable_irq(cs35l56->base.irq); 896 897 return 0; 898 } 899 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq); 900 901 int cs35l56_system_resume_no_irq(struct device *dev) 902 { 903 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 904 905 dev_dbg(dev, "system_resume_no_irq\n"); 906 907 /* 908 * WAKE interrupts unmask if the CS35L56 hibernates, which can cause 909 * spurious interrupts, and the interrupt line is normally shared. 910 * We can't check if our device is the source of an interrupt, and can't 911 * clear it, until it has fully resumed. Prevent this race by temporarily 912 * disabling the parent irq until we complete resume(). 913 */ 914 if (cs35l56->base.irq) 915 disable_irq(cs35l56->base.irq); 916 917 return 0; 918 } 919 EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq); 920 921 int cs35l56_system_resume_early(struct device *dev) 922 { 923 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 924 int ret; 925 926 dev_dbg(dev, "system_resume_early\n"); 927 928 /* Ensure a spec-compliant RESET pulse. */ 929 if (cs35l56->base.reset_gpio) { 930 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 931 cs35l56_wait_min_reset_pulse(); 932 } 933 934 /* Enable supplies before releasing RESET. */ 935 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 936 if (ret) { 937 dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret); 938 return ret; 939 } 940 941 /* Release shared RESET before drivers start resume(). */ 942 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1); 943 944 return 0; 945 } 946 EXPORT_SYMBOL_GPL(cs35l56_system_resume_early); 947 948 int cs35l56_system_resume(struct device *dev) 949 { 950 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 951 int ret; 952 953 dev_dbg(dev, "system_resume\n"); 954 955 /* 956 * We might have done a hard reset or the CS35L56 was power-cycled 957 * so wait for control port to be ready. 958 */ 959 cs35l56_wait_control_port_ready(); 960 961 /* Undo pm_runtime_force_suspend() before re-enabling the irq */ 962 ret = pm_runtime_force_resume(dev); 963 if (cs35l56->base.irq) 964 enable_irq(cs35l56->base.irq); 965 966 if (ret) 967 return ret; 968 969 /* Firmware won't have been loaded if the component hasn't probed */ 970 if (!cs35l56->component) 971 return 0; 972 973 ret = cs35l56_is_fw_reload_needed(&cs35l56->base); 974 dev_dbg(cs35l56->base.dev, "fw_reload_needed: %d\n", ret); 975 if (ret < 1) 976 return ret; 977 978 cs35l56->base.fw_patched = false; 979 wm_adsp_power_down(&cs35l56->dsp); 980 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 981 982 /* 983 * suspend_bias_off ensures we are now in BIAS_OFF so there will be 984 * a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching. 985 */ 986 987 return 0; 988 } 989 EXPORT_SYMBOL_GPL(cs35l56_system_resume); 990 991 static int cs35l56_dsp_init(struct cs35l56_private *cs35l56) 992 { 993 struct wm_adsp *dsp; 994 int ret; 995 996 cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp"); 997 if (!cs35l56->dsp_wq) 998 return -ENOMEM; 999 1000 INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work); 1001 1002 dsp = &cs35l56->dsp; 1003 cs35l56_init_cs_dsp(&cs35l56->base, &dsp->cs_dsp); 1004 dsp->part = "cs35l56"; 1005 dsp->fw = 12; 1006 dsp->wmfw_optional = true; 1007 1008 dev_dbg(cs35l56->base.dev, "DSP system name: '%s'\n", dsp->system_name); 1009 1010 ret = wm_halo_init(dsp); 1011 if (ret != 0) { 1012 dev_err(cs35l56->base.dev, "wm_halo_init failed\n"); 1013 return ret; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int cs35l56_acpi_get_name(struct cs35l56_private *cs35l56) 1020 { 1021 acpi_handle handle = ACPI_HANDLE(cs35l56->base.dev); 1022 const char *sub; 1023 1024 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1025 if (!handle) 1026 return 0; 1027 1028 sub = acpi_get_subsystem_id(handle); 1029 if (IS_ERR(sub)) { 1030 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1031 if (PTR_ERR(sub) == -ENODATA) 1032 return 0; 1033 else 1034 return PTR_ERR(sub); 1035 } 1036 1037 cs35l56->dsp.system_name = sub; 1038 dev_dbg(cs35l56->base.dev, "Subsystem ID: %s\n", cs35l56->dsp.system_name); 1039 1040 return 0; 1041 } 1042 1043 int cs35l56_common_probe(struct cs35l56_private *cs35l56) 1044 { 1045 int ret; 1046 1047 init_completion(&cs35l56->init_completion); 1048 mutex_init(&cs35l56->base.irq_lock); 1049 1050 dev_set_drvdata(cs35l56->base.dev, cs35l56); 1051 1052 cs35l56_fill_supply_names(cs35l56->supplies); 1053 ret = devm_regulator_bulk_get(cs35l56->base.dev, ARRAY_SIZE(cs35l56->supplies), 1054 cs35l56->supplies); 1055 if (ret != 0) 1056 return dev_err_probe(cs35l56->base.dev, ret, "Failed to request supplies\n"); 1057 1058 /* Reset could be controlled by the BIOS or shared by multiple amps */ 1059 cs35l56->base.reset_gpio = devm_gpiod_get_optional(cs35l56->base.dev, "reset", 1060 GPIOD_OUT_LOW); 1061 if (IS_ERR(cs35l56->base.reset_gpio)) { 1062 ret = PTR_ERR(cs35l56->base.reset_gpio); 1063 /* 1064 * If RESET is shared the first amp to probe will grab the reset 1065 * line and reset all the amps 1066 */ 1067 if (ret != -EBUSY) 1068 return dev_err_probe(cs35l56->base.dev, ret, "Failed to get reset GPIO\n"); 1069 1070 dev_info(cs35l56->base.dev, "Reset GPIO busy, assume shared reset\n"); 1071 cs35l56->base.reset_gpio = NULL; 1072 } 1073 1074 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1075 if (ret != 0) 1076 return dev_err_probe(cs35l56->base.dev, ret, "Failed to enable supplies\n"); 1077 1078 if (cs35l56->base.reset_gpio) { 1079 /* ACPI can override GPIOD_OUT_LOW flag so force it to start low */ 1080 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 1081 cs35l56_wait_min_reset_pulse(); 1082 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1); 1083 } 1084 1085 ret = cs35l56_acpi_get_name(cs35l56); 1086 if (ret != 0) 1087 goto err; 1088 1089 ret = cs35l56_dsp_init(cs35l56); 1090 if (ret < 0) { 1091 dev_err_probe(cs35l56->base.dev, ret, "DSP init failed\n"); 1092 goto err; 1093 } 1094 1095 ret = devm_snd_soc_register_component(cs35l56->base.dev, 1096 &soc_component_dev_cs35l56, 1097 cs35l56_dai, ARRAY_SIZE(cs35l56_dai)); 1098 if (ret < 0) { 1099 dev_err_probe(cs35l56->base.dev, ret, "Register codec failed\n"); 1100 goto err; 1101 } 1102 1103 return 0; 1104 1105 err: 1106 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 1107 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1108 1109 return ret; 1110 } 1111 EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE); 1112 1113 int cs35l56_init(struct cs35l56_private *cs35l56) 1114 { 1115 int ret; 1116 1117 /* 1118 * Check whether the actions associated with soft reset or one time 1119 * init need to be performed. 1120 */ 1121 if (cs35l56->soft_resetting) 1122 goto post_soft_reset; 1123 1124 if (cs35l56->base.init_done) 1125 return 0; 1126 1127 pm_runtime_set_autosuspend_delay(cs35l56->base.dev, 100); 1128 pm_runtime_use_autosuspend(cs35l56->base.dev); 1129 pm_runtime_set_active(cs35l56->base.dev); 1130 pm_runtime_enable(cs35l56->base.dev); 1131 1132 ret = cs35l56_hw_init(&cs35l56->base); 1133 if (ret < 0) 1134 return ret; 1135 1136 /* Populate the DSP information with the revision and security state */ 1137 cs35l56->dsp.part = devm_kasprintf(cs35l56->base.dev, GFP_KERNEL, "cs35l56%s-%02x", 1138 cs35l56->base.secured ? "s" : "", cs35l56->base.rev); 1139 if (!cs35l56->dsp.part) 1140 return -ENOMEM; 1141 1142 if (!cs35l56->base.reset_gpio) { 1143 dev_dbg(cs35l56->base.dev, "No reset gpio: using soft reset\n"); 1144 cs35l56->soft_resetting = true; 1145 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral); 1146 if (cs35l56->sdw_peripheral) { 1147 /* Keep alive while we wait for re-enumeration */ 1148 pm_runtime_get_noresume(cs35l56->base.dev); 1149 return 0; 1150 } 1151 } 1152 1153 post_soft_reset: 1154 if (cs35l56->soft_resetting) { 1155 cs35l56->soft_resetting = false; 1156 1157 /* Done re-enumerating after one-time init so release the keep-alive */ 1158 if (cs35l56->sdw_peripheral && !cs35l56->base.init_done) 1159 pm_runtime_put_noidle(cs35l56->base.dev); 1160 1161 regcache_mark_dirty(cs35l56->base.regmap); 1162 ret = cs35l56_wait_for_firmware_boot(&cs35l56->base); 1163 if (ret) 1164 return ret; 1165 1166 dev_dbg(cs35l56->base.dev, "Firmware rebooted after soft reset\n"); 1167 } 1168 1169 /* Disable auto-hibernate so that runtime_pm has control */ 1170 ret = cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1171 if (ret) 1172 return ret; 1173 1174 ret = cs35l56_set_patch(&cs35l56->base); 1175 if (ret) 1176 return ret; 1177 1178 /* Registers could be dirty after soft reset or SoundWire enumeration */ 1179 regcache_sync(cs35l56->base.regmap); 1180 1181 cs35l56->base.init_done = true; 1182 complete(&cs35l56->init_completion); 1183 1184 return 0; 1185 } 1186 EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE); 1187 1188 void cs35l56_remove(struct cs35l56_private *cs35l56) 1189 { 1190 cs35l56->base.init_done = false; 1191 1192 /* 1193 * WAKE IRQs unmask if CS35L56 hibernates so free the handler to 1194 * prevent it racing with remove(). 1195 */ 1196 if (cs35l56->base.irq) 1197 devm_free_irq(cs35l56->base.dev, cs35l56->base.irq, &cs35l56->base); 1198 1199 flush_workqueue(cs35l56->dsp_wq); 1200 destroy_workqueue(cs35l56->dsp_wq); 1201 1202 pm_runtime_suspend(cs35l56->base.dev); 1203 pm_runtime_disable(cs35l56->base.dev); 1204 1205 regcache_cache_only(cs35l56->base.regmap, true); 1206 1207 kfree(cs35l56->dsp.system_name); 1208 1209 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 1210 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1211 } 1212 EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE); 1213 1214 const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = { 1215 SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend_i2c_spi, cs35l56_runtime_resume_i2c_spi, NULL) 1216 SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume) 1217 LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early) 1218 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq) 1219 }; 1220 EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE); 1221 1222 MODULE_DESCRIPTION("ASoC CS35L56 driver"); 1223 MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED); 1224 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1225 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1226 MODULE_LICENSE("GPL"); 1227