14fa9c49fSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 27ac6653aSJeff Kirsher /******************************************************************************* 37ac6653aSJeff Kirsher Copyright (C) 2007-2009 STMicroelectronics Ltd 47ac6653aSJeff Kirsher 57ac6653aSJeff Kirsher 67ac6653aSJeff Kirsher Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 77ac6653aSJeff Kirsher *******************************************************************************/ 87ac6653aSJeff Kirsher 9bd4242dfSRayagond Kokatanur #ifndef __STMMAC_H__ 10bd4242dfSRayagond Kokatanur #define __STMMAC_H__ 11bd4242dfSRayagond Kokatanur 12bfab27a1SGiuseppe CAVALLARO #define STMMAC_RESOURCE_NAME "stmmaceth" 1306bce7ddSAlexandre TORGUE #define DRV_MODULE_VERSION "Jan_2016" 14ba1377ffSGiuseppe CAVALLARO 15ba1377ffSGiuseppe CAVALLARO #include <linux/clk.h> 163cd1cfcbSJose Abreu #include <linux/if_vlan.h> 177ac6653aSJeff Kirsher #include <linux/stmmac.h> 18eeef2f6bSJose Abreu #include <linux/phylink.h> 1933d5e332SGiuseppe CAVALLARO #include <linux/pci.h> 207ac6653aSJeff Kirsher #include "common.h" 2192ba6888SRayagond Kokatanur #include <linux/ptp_clock_kernel.h> 22d6228b7cSArtem Panfilov #include <linux/net_tstamp.h> 23c5e4ddbdSChen-Yu Tsai #include <linux/reset.h> 242af6106aSJose Abreu #include <net/page_pool.h> 257ac6653aSJeff Kirsher 26e56788cfSJoachim Eastwood struct stmmac_resources { 27e56788cfSJoachim Eastwood void __iomem *addr; 28e56788cfSJoachim Eastwood const char *mac; 29e56788cfSJoachim Eastwood int wol_irq; 30e56788cfSJoachim Eastwood int lpi_irq; 31e56788cfSJoachim Eastwood int irq; 32e56788cfSJoachim Eastwood }; 33e56788cfSJoachim Eastwood 34362b37beSGiuseppe CAVALLARO struct stmmac_tx_info { 35362b37beSGiuseppe CAVALLARO dma_addr_t buf; 36362b37beSGiuseppe CAVALLARO bool map_as_page; 37553e2ab3SGiuseppe Cavallaro unsigned len; 382a6d8e17SGiuseppe Cavallaro bool last_segment; 3996951366SGiuseppe Cavallaro bool is_jumbo; 40362b37beSGiuseppe CAVALLARO }; 41362b37beSGiuseppe CAVALLARO 42ce736788SJoao Pinto /* Frequently used values are kept adjacent for cache effect */ 43ce736788SJoao Pinto struct stmmac_tx_queue { 448fce3331SJose Abreu u32 tx_count_frames; 458fce3331SJose Abreu struct timer_list txtimer; 46ce736788SJoao Pinto u32 queue_index; 47ce736788SJoao Pinto struct stmmac_priv *priv_data; 48ce736788SJoao Pinto struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 49ce736788SJoao Pinto struct dma_desc *dma_tx; 50ce736788SJoao Pinto struct sk_buff **tx_skbuff; 51ce736788SJoao Pinto struct stmmac_tx_info *tx_skbuff_dma; 52ce736788SJoao Pinto unsigned int cur_tx; 53ce736788SJoao Pinto unsigned int dirty_tx; 54ce736788SJoao Pinto dma_addr_t dma_tx_phy; 55ce736788SJoao Pinto u32 tx_tail_addr; 568d212a9eSNiklas Cassel u32 mss; 57ce736788SJoao Pinto }; 58ce736788SJoao Pinto 592af6106aSJose Abreu struct stmmac_rx_buffer { 602af6106aSJose Abreu struct page *page; 61*67afd6d1SJose Abreu struct page *sec_page; 622af6106aSJose Abreu dma_addr_t addr; 63*67afd6d1SJose Abreu dma_addr_t sec_addr; 642af6106aSJose Abreu }; 652af6106aSJose Abreu 6654139cf3SJoao Pinto struct stmmac_rx_queue { 67d429b66eSJose Abreu u32 rx_count_frames; 6854139cf3SJoao Pinto u32 queue_index; 692af6106aSJose Abreu struct page_pool *page_pool; 702af6106aSJose Abreu struct stmmac_rx_buffer *buf_pool; 7154139cf3SJoao Pinto struct stmmac_priv *priv_data; 7254139cf3SJoao Pinto struct dma_extended_desc *dma_erx; 7354139cf3SJoao Pinto struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 7454139cf3SJoao Pinto unsigned int cur_rx; 7554139cf3SJoao Pinto unsigned int dirty_rx; 7654139cf3SJoao Pinto u32 rx_zeroc_thresh; 7754139cf3SJoao Pinto dma_addr_t dma_rx_phy; 7854139cf3SJoao Pinto u32 rx_tail_addr; 79ec222003SJose Abreu unsigned int state_saved; 80ec222003SJose Abreu struct { 81ec222003SJose Abreu struct sk_buff *skb; 82ec222003SJose Abreu unsigned int len; 83ec222003SJose Abreu unsigned int error; 84ec222003SJose Abreu } state; 858fce3331SJose Abreu }; 868fce3331SJose Abreu 878fce3331SJose Abreu struct stmmac_channel { 884ccb4585SJose Abreu struct napi_struct rx_napi ____cacheline_aligned_in_smp; 894ccb4585SJose Abreu struct napi_struct tx_napi ____cacheline_aligned_in_smp; 908fce3331SJose Abreu struct stmmac_priv *priv_data; 918fce3331SJose Abreu u32 index; 9254139cf3SJoao Pinto }; 9354139cf3SJoao Pinto 944dbbe8ddSJose Abreu struct stmmac_tc_entry { 954dbbe8ddSJose Abreu bool in_use; 964dbbe8ddSJose Abreu bool in_hw; 974dbbe8ddSJose Abreu bool is_last; 984dbbe8ddSJose Abreu bool is_frag; 994dbbe8ddSJose Abreu void *frag_ptr; 1004dbbe8ddSJose Abreu unsigned int table_pos; 1014dbbe8ddSJose Abreu u32 handle; 1024dbbe8ddSJose Abreu u32 prio; 1034dbbe8ddSJose Abreu struct { 1044dbbe8ddSJose Abreu u32 match_data; 1054dbbe8ddSJose Abreu u32 match_en; 1064dbbe8ddSJose Abreu u8 af:1; 1074dbbe8ddSJose Abreu u8 rf:1; 1084dbbe8ddSJose Abreu u8 im:1; 1094dbbe8ddSJose Abreu u8 nc:1; 1104dbbe8ddSJose Abreu u8 res1:4; 1114dbbe8ddSJose Abreu u8 frame_offset; 1124dbbe8ddSJose Abreu u8 ok_index; 1134dbbe8ddSJose Abreu u8 dma_ch_no; 1144dbbe8ddSJose Abreu u32 res2; 1154dbbe8ddSJose Abreu } __packed val; 1164dbbe8ddSJose Abreu }; 1174dbbe8ddSJose Abreu 1189a8a02c9SJose Abreu #define STMMAC_PPS_MAX 4 1199a8a02c9SJose Abreu struct stmmac_pps_cfg { 1209a8a02c9SJose Abreu bool available; 1219a8a02c9SJose Abreu struct timespec64 start; 1229a8a02c9SJose Abreu struct timespec64 period; 1239a8a02c9SJose Abreu }; 1249a8a02c9SJose Abreu 12576067459SJose Abreu struct stmmac_rss { 12676067459SJose Abreu int enable; 12776067459SJose Abreu u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 12876067459SJose Abreu u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 12976067459SJose Abreu }; 13076067459SJose Abreu 1317ac6653aSJeff Kirsher struct stmmac_priv { 1327ac6653aSJeff Kirsher /* Frequently used values are kept adjacent for cache effect */ 1331bb6dea8SGiuseppe CAVALLARO u32 tx_coal_frames; 1341bb6dea8SGiuseppe CAVALLARO u32 tx_coal_timer; 135d429b66eSJose Abreu u32 rx_coal_frames; 136ce736788SJoao Pinto 1377ac6653aSJeff Kirsher int tx_coalesce; 1381bb6dea8SGiuseppe CAVALLARO int hwts_tx_en; 1391bb6dea8SGiuseppe CAVALLARO bool tx_path_in_lpi_mode; 140f748be53SAlexandre TORGUE bool tso; 141*67afd6d1SJose Abreu int sph; 1427ac6653aSJeff Kirsher 1437ac6653aSJeff Kirsher unsigned int dma_buf_sz; 14422ad3838SGiuseppe Cavallaro unsigned int rx_copybreak; 1451bb6dea8SGiuseppe CAVALLARO u32 rx_riwt; 1461bb6dea8SGiuseppe CAVALLARO int hwts_rx_en; 1475bacd778SLABBE Corentin 1481bb6dea8SGiuseppe CAVALLARO void __iomem *ioaddr; 1491bb6dea8SGiuseppe CAVALLARO struct net_device *dev; 1507ac6653aSJeff Kirsher struct device *device; 1517ac6653aSJeff Kirsher struct mac_device_info *hw; 1527cfde0afSJose Abreu int (*hwif_quirks)(struct stmmac_priv *priv); 15329555fa3SThierry Reding struct mutex lock; 1547ac6653aSJeff Kirsher 15554139cf3SJoao Pinto /* RX Queue */ 15654139cf3SJoao Pinto struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 15754139cf3SJoao Pinto 158ce736788SJoao Pinto /* TX Queue */ 159ce736788SJoao Pinto struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 160ce736788SJoao Pinto 1618fce3331SJose Abreu /* Generic channel for NAPI */ 1628fce3331SJose Abreu struct stmmac_channel channel[STMMAC_CH_MAX]; 1638fce3331SJose Abreu 1647ac6653aSJeff Kirsher int speed; 1657ac6653aSJeff Kirsher unsigned int flow_ctrl; 1667ac6653aSJeff Kirsher unsigned int pause; 1677ac6653aSJeff Kirsher struct mii_bus *mii; 1687ac6653aSJeff Kirsher int mii_irq[PHY_MAX_ADDR]; 1697ac6653aSJeff Kirsher 170eeef2f6bSJose Abreu struct phylink_config phylink_config; 171eeef2f6bSJose Abreu struct phylink *phylink; 172eeef2f6bSJose Abreu 1731bb6dea8SGiuseppe CAVALLARO struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 1748bf993a5SJose Abreu struct stmmac_safety_stats sstats; 1751bb6dea8SGiuseppe CAVALLARO struct plat_stmmacenet_data *plat; 1761bb6dea8SGiuseppe CAVALLARO struct dma_features dma_cap; 1771bb6dea8SGiuseppe CAVALLARO struct stmmac_counters mmc; 1781bb6dea8SGiuseppe CAVALLARO int hw_cap_support; 1791bb6dea8SGiuseppe CAVALLARO int synopsys_id; 1807ac6653aSJeff Kirsher u32 msg_enable; 1817ac6653aSJeff Kirsher int wolopts; 1823172d3afSDeepak Sikri int wol_irq; 183cd7201f4SGiuseppe CAVALLARO int clk_csr; 184d765955dSGiuseppe CAVALLARO struct timer_list eee_ctrl_timer; 185d765955dSGiuseppe CAVALLARO int lpi_irq; 186d765955dSGiuseppe CAVALLARO int eee_enabled; 187d765955dSGiuseppe CAVALLARO int eee_active; 188d765955dSGiuseppe CAVALLARO int tx_lpi_timer; 1894a7d666aSGiuseppe CAVALLARO unsigned int mode; 1905f0456b4SJose Abreu unsigned int chain_mode; 191c24602efSGiuseppe CAVALLARO int extend_desc; 192d6228b7cSArtem Panfilov struct hwtstamp_config tstamp_config; 19392ba6888SRayagond Kokatanur struct ptp_clock *ptp_clock; 19492ba6888SRayagond Kokatanur struct ptp_clock_info ptp_clock_ops; 1951bb6dea8SGiuseppe CAVALLARO unsigned int default_addend; 1969a8a02c9SJose Abreu u32 sub_second_inc; 1979a8a02c9SJose Abreu u32 systime_flags; 1981bb6dea8SGiuseppe CAVALLARO u32 adv_ts; 1991bb6dea8SGiuseppe CAVALLARO int use_riwt; 20089f7f2cfSSrinivas Kandagatla int irq_wake; 20192ba6888SRayagond Kokatanur spinlock_t ptp_lock; 20236ff7c1eSAlexandre TORGUE void __iomem *mmcaddr; 203ba1ffd74SGiuseppe CAVALLARO void __iomem *ptpaddr; 2043cd1cfcbSJose Abreu unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 205466c5ac8SMathieu Olivari 206466c5ac8SMathieu Olivari #ifdef CONFIG_DEBUG_FS 207466c5ac8SMathieu Olivari struct dentry *dbgfs_dir; 208466c5ac8SMathieu Olivari #endif 20934877a15SJose Abreu 21034877a15SJose Abreu unsigned long state; 21134877a15SJose Abreu struct workqueue_struct *wq; 21234877a15SJose Abreu struct work_struct service_task; 2134dbbe8ddSJose Abreu 2144dbbe8ddSJose Abreu /* TC Handling */ 2154dbbe8ddSJose Abreu unsigned int tc_entries_max; 2164dbbe8ddSJose Abreu unsigned int tc_off_max; 2174dbbe8ddSJose Abreu struct stmmac_tc_entry *tc_entries; 2189a8a02c9SJose Abreu 2199a8a02c9SJose Abreu /* Pulse Per Second output */ 2209a8a02c9SJose Abreu struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 22176067459SJose Abreu 22276067459SJose Abreu /* Receive Side Scaling */ 22376067459SJose Abreu struct stmmac_rss rss; 22434877a15SJose Abreu }; 22534877a15SJose Abreu 22634877a15SJose Abreu enum stmmac_state { 22734877a15SJose Abreu STMMAC_DOWN, 22834877a15SJose Abreu STMMAC_RESET_REQUESTED, 22934877a15SJose Abreu STMMAC_RESETING, 23034877a15SJose Abreu STMMAC_SERVICE_SCHED, 2317ac6653aSJeff Kirsher }; 2327ac6653aSJeff Kirsher 233d6cc64efSJoe Perches int stmmac_mdio_unregister(struct net_device *ndev); 234d6cc64efSJoe Perches int stmmac_mdio_register(struct net_device *ndev); 235073752aaSSrinivas Kandagatla int stmmac_mdio_reset(struct mii_bus *mii); 236d6cc64efSJoe Perches void stmmac_set_ethtool_ops(struct net_device *netdev); 237915af656SAndy Shevchenko 238c30a70d3SGiuseppe CAVALLARO void stmmac_ptp_register(struct stmmac_priv *priv); 239d6cc64efSJoe Perches void stmmac_ptp_unregister(struct stmmac_priv *priv); 240f4e7bd81SJoachim Eastwood int stmmac_resume(struct device *dev); 241f4e7bd81SJoachim Eastwood int stmmac_suspend(struct device *dev); 242f4e7bd81SJoachim Eastwood int stmmac_dvr_remove(struct device *dev); 24315ffac73SJoachim Eastwood int stmmac_dvr_probe(struct device *device, 244cf3f047bSGiuseppe CAVALLARO struct plat_stmmacenet_data *plat_dat, 245e56788cfSJoachim Eastwood struct stmmac_resources *res); 246d765955dSGiuseppe CAVALLARO void stmmac_disable_eee_mode(struct stmmac_priv *priv); 247d765955dSGiuseppe CAVALLARO bool stmmac_eee_init(struct stmmac_priv *priv); 248ba1377ffSGiuseppe CAVALLARO 249091810dbSJose Abreu #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 250091810dbSJose Abreu void stmmac_selftest_run(struct net_device *dev, 251091810dbSJose Abreu struct ethtool_test *etest, u64 *buf); 252091810dbSJose Abreu void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 253091810dbSJose Abreu int stmmac_selftest_get_count(struct stmmac_priv *priv); 254091810dbSJose Abreu #else 255091810dbSJose Abreu static inline void stmmac_selftest_run(struct net_device *dev, 256091810dbSJose Abreu struct ethtool_test *etest, u64 *buf) 257091810dbSJose Abreu { 258091810dbSJose Abreu /* Not enabled */ 259091810dbSJose Abreu } 260091810dbSJose Abreu static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 261091810dbSJose Abreu u8 *data) 262091810dbSJose Abreu { 263091810dbSJose Abreu /* Not enabled */ 264091810dbSJose Abreu } 265091810dbSJose Abreu static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 266091810dbSJose Abreu { 267091810dbSJose Abreu return -EOPNOTSUPP; 268091810dbSJose Abreu } 269091810dbSJose Abreu #endif /* CONFIG_STMMAC_SELFTESTS */ 270091810dbSJose Abreu 271bd4242dfSRayagond Kokatanur #endif /* __STMMAC_H__ */ 272