17ac6653aSJeff Kirsher /******************************************************************************* 27ac6653aSJeff Kirsher Copyright (C) 2007-2009 STMicroelectronics Ltd 37ac6653aSJeff Kirsher 47ac6653aSJeff Kirsher This program is free software; you can redistribute it and/or modify it 57ac6653aSJeff Kirsher under the terms and conditions of the GNU General Public License, 67ac6653aSJeff Kirsher version 2, as published by the Free Software Foundation. 77ac6653aSJeff Kirsher 87ac6653aSJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 97ac6653aSJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 107ac6653aSJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 117ac6653aSJeff Kirsher more details. 127ac6653aSJeff Kirsher 137ac6653aSJeff Kirsher The full GNU General Public License is included in this distribution in 147ac6653aSJeff Kirsher the file called "COPYING". 157ac6653aSJeff Kirsher 167ac6653aSJeff Kirsher Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 177ac6653aSJeff Kirsher *******************************************************************************/ 187ac6653aSJeff Kirsher 19bd4242dfSRayagond Kokatanur #ifndef __STMMAC_H__ 20bd4242dfSRayagond Kokatanur #define __STMMAC_H__ 21bd4242dfSRayagond Kokatanur 22bfab27a1SGiuseppe CAVALLARO #define STMMAC_RESOURCE_NAME "stmmaceth" 2306bce7ddSAlexandre TORGUE #define DRV_MODULE_VERSION "Jan_2016" 24ba1377ffSGiuseppe CAVALLARO 25ba1377ffSGiuseppe CAVALLARO #include <linux/clk.h> 267ac6653aSJeff Kirsher #include <linux/stmmac.h> 27286a8372SGiuseppe CAVALLARO #include <linux/phy.h> 2833d5e332SGiuseppe CAVALLARO #include <linux/pci.h> 297ac6653aSJeff Kirsher #include "common.h" 3092ba6888SRayagond Kokatanur #include <linux/ptp_clock_kernel.h> 31c5e4ddbdSChen-Yu Tsai #include <linux/reset.h> 327ac6653aSJeff Kirsher 33e56788cfSJoachim Eastwood struct stmmac_resources { 34e56788cfSJoachim Eastwood void __iomem *addr; 35e56788cfSJoachim Eastwood const char *mac; 36e56788cfSJoachim Eastwood int wol_irq; 37e56788cfSJoachim Eastwood int lpi_irq; 38e56788cfSJoachim Eastwood int irq; 39e56788cfSJoachim Eastwood }; 40e56788cfSJoachim Eastwood 41362b37beSGiuseppe CAVALLARO struct stmmac_tx_info { 42362b37beSGiuseppe CAVALLARO dma_addr_t buf; 43362b37beSGiuseppe CAVALLARO bool map_as_page; 44553e2ab3SGiuseppe Cavallaro unsigned len; 452a6d8e17SGiuseppe Cavallaro bool last_segment; 4696951366SGiuseppe Cavallaro bool is_jumbo; 47362b37beSGiuseppe CAVALLARO }; 48362b37beSGiuseppe CAVALLARO 49ce736788SJoao Pinto /* Frequently used values are kept adjacent for cache effect */ 50ce736788SJoao Pinto struct stmmac_tx_queue { 51ce736788SJoao Pinto u32 queue_index; 52ce736788SJoao Pinto struct stmmac_priv *priv_data; 53ce736788SJoao Pinto struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 54ce736788SJoao Pinto struct dma_desc *dma_tx; 55ce736788SJoao Pinto struct sk_buff **tx_skbuff; 56ce736788SJoao Pinto struct stmmac_tx_info *tx_skbuff_dma; 57ce736788SJoao Pinto unsigned int cur_tx; 58ce736788SJoao Pinto unsigned int dirty_tx; 59ce736788SJoao Pinto dma_addr_t dma_tx_phy; 60ce736788SJoao Pinto u32 tx_tail_addr; 618d212a9eSNiklas Cassel u32 mss; 62ce736788SJoao Pinto }; 63ce736788SJoao Pinto 6454139cf3SJoao Pinto struct stmmac_rx_queue { 6554139cf3SJoao Pinto u32 queue_index; 6654139cf3SJoao Pinto struct stmmac_priv *priv_data; 6754139cf3SJoao Pinto struct dma_extended_desc *dma_erx; 6854139cf3SJoao Pinto struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 6954139cf3SJoao Pinto struct sk_buff **rx_skbuff; 7054139cf3SJoao Pinto dma_addr_t *rx_skbuff_dma; 7154139cf3SJoao Pinto unsigned int cur_rx; 7254139cf3SJoao Pinto unsigned int dirty_rx; 7354139cf3SJoao Pinto u32 rx_zeroc_thresh; 7454139cf3SJoao Pinto dma_addr_t dma_rx_phy; 7554139cf3SJoao Pinto u32 rx_tail_addr; 76c22a3f48SJoao Pinto struct napi_struct napi ____cacheline_aligned_in_smp; 7754139cf3SJoao Pinto }; 7854139cf3SJoao Pinto 79*4dbbe8ddSJose Abreu struct stmmac_tc_entry { 80*4dbbe8ddSJose Abreu bool in_use; 81*4dbbe8ddSJose Abreu bool in_hw; 82*4dbbe8ddSJose Abreu bool is_last; 83*4dbbe8ddSJose Abreu bool is_frag; 84*4dbbe8ddSJose Abreu void *frag_ptr; 85*4dbbe8ddSJose Abreu unsigned int table_pos; 86*4dbbe8ddSJose Abreu u32 handle; 87*4dbbe8ddSJose Abreu u32 prio; 88*4dbbe8ddSJose Abreu struct { 89*4dbbe8ddSJose Abreu u32 match_data; 90*4dbbe8ddSJose Abreu u32 match_en; 91*4dbbe8ddSJose Abreu u8 af:1; 92*4dbbe8ddSJose Abreu u8 rf:1; 93*4dbbe8ddSJose Abreu u8 im:1; 94*4dbbe8ddSJose Abreu u8 nc:1; 95*4dbbe8ddSJose Abreu u8 res1:4; 96*4dbbe8ddSJose Abreu u8 frame_offset; 97*4dbbe8ddSJose Abreu u8 ok_index; 98*4dbbe8ddSJose Abreu u8 dma_ch_no; 99*4dbbe8ddSJose Abreu u32 res2; 100*4dbbe8ddSJose Abreu } __packed val; 101*4dbbe8ddSJose Abreu }; 102*4dbbe8ddSJose Abreu 1037ac6653aSJeff Kirsher struct stmmac_priv { 1047ac6653aSJeff Kirsher /* Frequently used values are kept adjacent for cache effect */ 1051bb6dea8SGiuseppe CAVALLARO u32 tx_count_frames; 1061bb6dea8SGiuseppe CAVALLARO u32 tx_coal_frames; 1071bb6dea8SGiuseppe CAVALLARO u32 tx_coal_timer; 108ce736788SJoao Pinto 1097ac6653aSJeff Kirsher int tx_coalesce; 1101bb6dea8SGiuseppe CAVALLARO int hwts_tx_en; 1111bb6dea8SGiuseppe CAVALLARO bool tx_path_in_lpi_mode; 1121bb6dea8SGiuseppe CAVALLARO struct timer_list txtimer; 113f748be53SAlexandre TORGUE bool tso; 1147ac6653aSJeff Kirsher 1157ac6653aSJeff Kirsher unsigned int dma_buf_sz; 11622ad3838SGiuseppe Cavallaro unsigned int rx_copybreak; 1171bb6dea8SGiuseppe CAVALLARO u32 rx_riwt; 1181bb6dea8SGiuseppe CAVALLARO int hwts_rx_en; 1195bacd778SLABBE Corentin 1201bb6dea8SGiuseppe CAVALLARO void __iomem *ioaddr; 1211bb6dea8SGiuseppe CAVALLARO struct net_device *dev; 1227ac6653aSJeff Kirsher struct device *device; 1237ac6653aSJeff Kirsher struct mac_device_info *hw; 1241bb6dea8SGiuseppe CAVALLARO spinlock_t lock; 1257ac6653aSJeff Kirsher 12654139cf3SJoao Pinto /* RX Queue */ 12754139cf3SJoao Pinto struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 12854139cf3SJoao Pinto 129ce736788SJoao Pinto /* TX Queue */ 130ce736788SJoao Pinto struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 131ce736788SJoao Pinto 1324d869b03SLABBE Corentin bool oldlink; 1337ac6653aSJeff Kirsher int speed; 1347ac6653aSJeff Kirsher int oldduplex; 1357ac6653aSJeff Kirsher unsigned int flow_ctrl; 1367ac6653aSJeff Kirsher unsigned int pause; 1377ac6653aSJeff Kirsher struct mii_bus *mii; 1387ac6653aSJeff Kirsher int mii_irq[PHY_MAX_ADDR]; 1397ac6653aSJeff Kirsher 1401bb6dea8SGiuseppe CAVALLARO struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 1418bf993a5SJose Abreu struct stmmac_safety_stats sstats; 1421bb6dea8SGiuseppe CAVALLARO struct plat_stmmacenet_data *plat; 1431bb6dea8SGiuseppe CAVALLARO struct dma_features dma_cap; 1441bb6dea8SGiuseppe CAVALLARO struct stmmac_counters mmc; 1451bb6dea8SGiuseppe CAVALLARO int hw_cap_support; 1461bb6dea8SGiuseppe CAVALLARO int synopsys_id; 1477ac6653aSJeff Kirsher u32 msg_enable; 1487ac6653aSJeff Kirsher int wolopts; 1493172d3afSDeepak Sikri int wol_irq; 150cd7201f4SGiuseppe CAVALLARO int clk_csr; 151d765955dSGiuseppe CAVALLARO struct timer_list eee_ctrl_timer; 152d765955dSGiuseppe CAVALLARO int lpi_irq; 153d765955dSGiuseppe CAVALLARO int eee_enabled; 154d765955dSGiuseppe CAVALLARO int eee_active; 155d765955dSGiuseppe CAVALLARO int tx_lpi_timer; 1564a7d666aSGiuseppe CAVALLARO unsigned int mode; 1575f0456b4SJose Abreu unsigned int chain_mode; 158c24602efSGiuseppe CAVALLARO int extend_desc; 15992ba6888SRayagond Kokatanur struct ptp_clock *ptp_clock; 16092ba6888SRayagond Kokatanur struct ptp_clock_info ptp_clock_ops; 1611bb6dea8SGiuseppe CAVALLARO unsigned int default_addend; 1621bb6dea8SGiuseppe CAVALLARO u32 adv_ts; 1631bb6dea8SGiuseppe CAVALLARO int use_riwt; 16489f7f2cfSSrinivas Kandagatla int irq_wake; 16592ba6888SRayagond Kokatanur spinlock_t ptp_lock; 16636ff7c1eSAlexandre TORGUE void __iomem *mmcaddr; 167ba1ffd74SGiuseppe CAVALLARO void __iomem *ptpaddr; 168466c5ac8SMathieu Olivari 169466c5ac8SMathieu Olivari #ifdef CONFIG_DEBUG_FS 170466c5ac8SMathieu Olivari struct dentry *dbgfs_dir; 171466c5ac8SMathieu Olivari struct dentry *dbgfs_rings_status; 172466c5ac8SMathieu Olivari struct dentry *dbgfs_dma_cap; 173466c5ac8SMathieu Olivari #endif 17434877a15SJose Abreu 17534877a15SJose Abreu unsigned long state; 17634877a15SJose Abreu struct workqueue_struct *wq; 17734877a15SJose Abreu struct work_struct service_task; 178*4dbbe8ddSJose Abreu 179*4dbbe8ddSJose Abreu /* TC Handling */ 180*4dbbe8ddSJose Abreu unsigned int tc_entries_max; 181*4dbbe8ddSJose Abreu unsigned int tc_off_max; 182*4dbbe8ddSJose Abreu struct stmmac_tc_entry *tc_entries; 18334877a15SJose Abreu }; 18434877a15SJose Abreu 18534877a15SJose Abreu enum stmmac_state { 18634877a15SJose Abreu STMMAC_DOWN, 18734877a15SJose Abreu STMMAC_RESET_REQUESTED, 18834877a15SJose Abreu STMMAC_RESETING, 18934877a15SJose Abreu STMMAC_SERVICE_SCHED, 1907ac6653aSJeff Kirsher }; 1917ac6653aSJeff Kirsher 192d6cc64efSJoe Perches int stmmac_mdio_unregister(struct net_device *ndev); 193d6cc64efSJoe Perches int stmmac_mdio_register(struct net_device *ndev); 194073752aaSSrinivas Kandagatla int stmmac_mdio_reset(struct mii_bus *mii); 195d6cc64efSJoe Perches void stmmac_set_ethtool_ops(struct net_device *netdev); 196915af656SAndy Shevchenko 197c30a70d3SGiuseppe CAVALLARO void stmmac_ptp_register(struct stmmac_priv *priv); 198d6cc64efSJoe Perches void stmmac_ptp_unregister(struct stmmac_priv *priv); 199f4e7bd81SJoachim Eastwood int stmmac_resume(struct device *dev); 200f4e7bd81SJoachim Eastwood int stmmac_suspend(struct device *dev); 201f4e7bd81SJoachim Eastwood int stmmac_dvr_remove(struct device *dev); 20215ffac73SJoachim Eastwood int stmmac_dvr_probe(struct device *device, 203cf3f047bSGiuseppe CAVALLARO struct plat_stmmacenet_data *plat_dat, 204e56788cfSJoachim Eastwood struct stmmac_resources *res); 205d765955dSGiuseppe CAVALLARO void stmmac_disable_eee_mode(struct stmmac_priv *priv); 206d765955dSGiuseppe CAVALLARO bool stmmac_eee_init(struct stmmac_priv *priv); 207ba1377ffSGiuseppe CAVALLARO 208bd4242dfSRayagond Kokatanur #endif /* __STMMAC_H__ */ 209