1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool/types.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE 512 36 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 37 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 38 #define MTK_DMA_DUMMY_DESC 0xffffffff 39 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 40 NETIF_MSG_PROBE | \ 41 NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_IFDOWN | \ 44 NETIF_MSG_IFUP | \ 45 NETIF_MSG_RX_ERR | \ 46 NETIF_MSG_TX_ERR) 47 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 48 NETIF_F_RXCSUM | \ 49 NETIF_F_HW_VLAN_CTAG_TX | \ 50 NETIF_F_SG | NETIF_F_TSO | \ 51 NETIF_F_TSO6 | \ 52 NETIF_F_IPV6_CSUM |\ 53 NETIF_F_HW_TC) 54 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 55 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 56 57 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 58 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 59 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 60 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 61 62 #define MTK_QRX_OFFSET 0x10 63 64 #define MTK_MAX_RX_RING_NUM 4 65 #define MTK_HW_LRO_DMA_SIZE 8 66 67 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 68 #define MTK_MAX_LRO_IP_CNT 2 69 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 70 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 71 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 72 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 73 #define MTK_HW_LRO_MAX_AGG_CNT 64 74 #define MTK_HW_LRO_BW_THRE 3000 75 #define MTK_HW_LRO_REPLACE_DELTA 1000 76 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 77 78 /* Frame Engine Global Configuration */ 79 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) 80 #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) 81 82 /* Frame Engine Global Reset Register */ 83 #define MTK_RST_GL 0x04 84 #define RST_GL_PSE BIT(0) 85 86 /* Frame Engine Interrupt Status Register */ 87 #define MTK_INT_STATUS2 0x08 88 #define MTK_FE_INT_ENABLE 0x0c 89 #define MTK_FE_INT_FQ_EMPTY BIT(8) 90 #define MTK_FE_INT_TSO_FAIL BIT(12) 91 #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 92 #define MTK_FE_INT_TSO_ALIGN BIT(14) 93 #define MTK_FE_INT_RFIFO_OV BIT(18) 94 #define MTK_FE_INT_RFIFO_UF BIT(19) 95 #define MTK_GDM1_AF BIT(28) 96 #define MTK_GDM2_AF BIT(29) 97 98 /* PDMA HW LRO Alter Flow Timer Register */ 99 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 100 101 /* Frame Engine Interrupt Grouping Register */ 102 #define MTK_FE_INT_GRP 0x20 103 104 /* CDMP Ingress Control Register */ 105 #define MTK_CDMQ_IG_CTRL 0x1400 106 #define MTK_CDMQ_STAG_EN BIT(0) 107 108 /* CDMQ Exgress Control Register */ 109 #define MTK_CDMQ_EG_CTRL 0x1404 110 111 /* CDMP Ingress Control Register */ 112 #define MTK_CDMP_IG_CTRL 0x400 113 #define MTK_CDMP_STAG_EN BIT(0) 114 115 /* CDMP Exgress Control Register */ 116 #define MTK_CDMP_EG_CTRL 0x404 117 118 /* GDM Exgress Control Register */ 119 #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 120 0x540 : 0x500 + (_x * 0x1000); }) 121 #define MTK_GDMA_SPECIAL_TAG BIT(24) 122 #define MTK_GDMA_ICS_EN BIT(22) 123 #define MTK_GDMA_TCS_EN BIT(21) 124 #define MTK_GDMA_UCS_EN BIT(20) 125 #define MTK_GDMA_STRP_CRC BIT(16) 126 #define MTK_GDMA_TO_PDMA 0x0 127 #define MTK_GDMA_DROP_ALL 0x7777 128 129 /* GDM Egress Control Register */ 130 #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 131 0x544 : 0x504 + (_x * 0x1000); }) 132 #define MTK_GDMA_XGDM_SEL BIT(31) 133 134 /* Unicast Filter MAC Address Register - Low */ 135 #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 136 0x548 : 0x508 + (_x * 0x1000); }) 137 138 /* Unicast Filter MAC Address Register - High */ 139 #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 140 0x54C : 0x50C + (_x * 0x1000); }) 141 142 /* Internal SRAM offset */ 143 #define MTK_ETH_SRAM_OFFSET 0x40000 144 145 /* FE global misc reg*/ 146 #define MTK_FE_GLO_MISC 0x124 147 148 /* PSE Free Queue Flow Control */ 149 #define PSE_FQFC_CFG1 0x100 150 #define PSE_FQFC_CFG2 0x104 151 #define PSE_DROP_CFG 0x108 152 #define PSE_PPE0_DROP 0x110 153 154 /* PSE Input Queue Reservation Register*/ 155 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 156 157 /* PSE Output Queue Threshold Register*/ 158 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 159 160 /* GDM and CDM Threshold */ 161 #define MTK_GDM2_THRES 0x1530 162 #define MTK_CDMW0_THRES 0x164c 163 #define MTK_CDMW1_THRES 0x1650 164 #define MTK_CDME0_THRES 0x1654 165 #define MTK_CDME1_THRES 0x1658 166 #define MTK_CDMM_THRES 0x165c 167 168 /* PDMA HW LRO Control Registers */ 169 #define MTK_PDMA_LRO_CTRL_DW0 0x980 170 #define MTK_LRO_EN BIT(0) 171 #define MTK_L3_CKS_UPD_EN BIT(7) 172 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 173 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 174 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 175 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 176 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 177 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 178 179 #define MTK_PDMA_LRO_CTRL_DW1 0x984 180 #define MTK_PDMA_LRO_CTRL_DW2 0x988 181 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 182 #define MTK_ADMA_MODE BIT(15) 183 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 184 185 #define MTK_RX_DMA_LRO_EN BIT(8) 186 #define MTK_MULTI_EN BIT(10) 187 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 188 189 /* PDMA Global Configuration Register */ 190 #define MTK_PDMA_LRO_SDL 0x3000 191 #define MTK_RX_CFG_SDL_OFFSET 16 192 193 /* PDMA Reset Index Register */ 194 #define MTK_PST_DRX_IDX0 BIT(16) 195 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 196 197 /* PDMA Delay Interrupt Register */ 198 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 199 #define MTK_PDMA_DELAY_RX_EN BIT(15) 200 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 201 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 202 203 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 204 #define MTK_PDMA_DELAY_TX_EN BIT(31) 205 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 206 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 207 208 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 209 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 210 211 /* PDMA HW LRO Alter Flow Delta Register */ 212 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 213 214 /* PDMA HW LRO IP Setting Registers */ 215 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 216 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 217 #define MTK_RING_MYIP_VLD BIT(9) 218 219 /* PDMA HW LRO Ring Control Registers */ 220 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 221 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 222 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 223 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 224 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 225 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 226 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 227 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 228 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 229 #define MTK_RING_VLD BIT(8) 230 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 231 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 232 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 233 234 /* QDMA TX Queue Configuration Registers */ 235 #define MTK_QTX_OFFSET 0x10 236 #define QDMA_RES_THRES 4 237 238 /* QDMA Tx Queue Scheduler Configuration Registers */ 239 #define MTK_QTX_SCH_TX_SEL BIT(31) 240 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 241 242 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 243 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 244 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 245 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 246 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 247 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 248 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 249 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 250 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 251 252 /* QDMA TX Scheduler Rate Control Register */ 253 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 254 255 /* QDMA Global Configuration Register */ 256 #define MTK_RX_2B_OFFSET BIT(31) 257 #define MTK_RX_BT_32DWORDS (3 << 11) 258 #define MTK_NDP_CO_PRO BIT(10) 259 #define MTK_TX_WB_DDONE BIT(6) 260 #define MTK_TX_BT_32DWORDS (3 << 4) 261 #define MTK_RX_DMA_BUSY BIT(3) 262 #define MTK_TX_DMA_BUSY BIT(1) 263 #define MTK_RX_DMA_EN BIT(2) 264 #define MTK_TX_DMA_EN BIT(0) 265 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 266 267 /* QDMA V2 Global Configuration Register */ 268 #define MTK_CHK_DDONE_EN BIT(28) 269 #define MTK_DMAD_WR_WDONE BIT(26) 270 #define MTK_WCOMP_EN BIT(24) 271 #define MTK_RESV_BUF (0x40 << 16) 272 #define MTK_MUTLI_CNT (0x4 << 12) 273 #define MTK_LEAKY_BUCKET_EN BIT(11) 274 275 /* QDMA Flow Control Register */ 276 #define FC_THRES_DROP_MODE BIT(20) 277 #define FC_THRES_DROP_EN (7 << 16) 278 #define FC_THRES_MIN 0x4444 279 280 /* QDMA Interrupt Status Register */ 281 #define MTK_RX_DONE_DLY BIT(30) 282 #define MTK_TX_DONE_DLY BIT(28) 283 #define MTK_RX_DONE_INT3 BIT(19) 284 #define MTK_RX_DONE_INT2 BIT(18) 285 #define MTK_RX_DONE_INT1 BIT(17) 286 #define MTK_RX_DONE_INT0 BIT(16) 287 #define MTK_TX_DONE_INT3 BIT(3) 288 #define MTK_TX_DONE_INT2 BIT(2) 289 #define MTK_TX_DONE_INT1 BIT(1) 290 #define MTK_TX_DONE_INT0 BIT(0) 291 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 292 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 293 294 #define MTK_RX_DONE_INT_V2 BIT(14) 295 296 #define MTK_CDM_TXFIFO_RDY BIT(7) 297 298 /* QDMA Interrupt grouping registers */ 299 #define MTK_RLS_DONE_INT BIT(0) 300 301 /* QDMA TX NUM */ 302 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 303 #define MTK_QDMA_GMAC2_QID 8 304 305 #define MTK_TX_DMA_BUF_SHIFT 8 306 307 /* QDMA V2 descriptor txd6 */ 308 #define TX_DMA_INS_VLAN_V2 BIT(16) 309 /* QDMA V2 descriptor txd5 */ 310 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 311 #define TX_DMA_TSO_V2 BIT(31) 312 313 #define TX_DMA_SPTAG_V3 BIT(27) 314 315 /* QDMA V2 descriptor txd4 */ 316 #define TX_DMA_FPORT_SHIFT_V2 8 317 #define TX_DMA_FPORT_MASK_V2 0xf 318 #define TX_DMA_SWC_V2 BIT(30) 319 320 /* QDMA descriptor txd4 */ 321 #define TX_DMA_CHKSUM (0x7 << 29) 322 #define TX_DMA_TSO BIT(28) 323 #define TX_DMA_FPORT_SHIFT 25 324 #define TX_DMA_FPORT_MASK 0x7 325 #define TX_DMA_INS_VLAN BIT(16) 326 327 /* QDMA descriptor txd3 */ 328 #define TX_DMA_OWNER_CPU BIT(31) 329 #define TX_DMA_LS0 BIT(30) 330 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 331 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 332 #define TX_DMA_SWC BIT(14) 333 #define TX_DMA_PQID GENMASK(3, 0) 334 335 /* PDMA on MT7628 */ 336 #define TX_DMA_DONE BIT(31) 337 #define TX_DMA_LS1 BIT(14) 338 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 339 340 /* QDMA descriptor rxd2 */ 341 #define RX_DMA_DONE BIT(31) 342 #define RX_DMA_LSO BIT(30) 343 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 344 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 345 #define RX_DMA_VTAG BIT(15) 346 347 /* QDMA descriptor rxd3 */ 348 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 349 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 350 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 351 352 /* QDMA descriptor rxd4 */ 353 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 354 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 355 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 356 #define MTK_RXD4_ALG GENMASK(31, 22) 357 358 /* QDMA descriptor rxd4 */ 359 #define RX_DMA_L4_VALID BIT(24) 360 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 361 #define RX_DMA_SPECIAL_TAG BIT(22) 362 363 /* PDMA descriptor rxd5 */ 364 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 365 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 366 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 367 368 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 369 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 370 371 /* PDMA V2 descriptor rxd3 */ 372 #define RX_DMA_VTAG_V2 BIT(0) 373 #define RX_DMA_L4_VALID_V2 BIT(2) 374 375 /* PHY Polling and SMI Master Control registers */ 376 #define MTK_PPSC 0x10000 377 #define PPSC_MDC_CFG GENMASK(29, 24) 378 #define PPSC_MDC_TURBO BIT(20) 379 #define MDC_MAX_FREQ 25000000 380 #define MDC_MAX_DIVIDER 63 381 382 /* PHY Indirect Access Control registers */ 383 #define MTK_PHY_IAC 0x10004 384 #define PHY_IAC_ACCESS BIT(31) 385 #define PHY_IAC_REG_MASK GENMASK(29, 25) 386 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 387 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 388 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 389 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 390 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 391 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 392 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 393 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 394 #define PHY_IAC_START_MASK GENMASK(17, 16) 395 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 396 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 397 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 398 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 399 #define PHY_IAC_TIMEOUT HZ 400 401 #define MTK_MAC_MISC 0x1000c 402 #define MTK_MAC_MISC_V3 0x10010 403 #define MTK_MUX_TO_ESW BIT(0) 404 #define MISC_MDC_TURBO BIT(4) 405 406 /* XMAC status registers */ 407 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 408 #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 409 #define MTK_USXGMII_PCS_LINK BIT(8) 410 #define MTK_XGMAC_RX_FC BIT(5) 411 #define MTK_XGMAC_TX_FC BIT(4) 412 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 413 #define MTK_XGMAC_LINK_STS BIT(0) 414 415 /* GSW bridge registers */ 416 #define MTK_GSW_CFG (0x10080) 417 #define GSWTX_IPG_MASK GENMASK(19, 16) 418 #define GSWTX_IPG_SHIFT 16 419 #define GSWRX_IPG_MASK GENMASK(3, 0) 420 #define GSWRX_IPG_SHIFT 0 421 #define GSW_IPG_11 11 422 423 /* Mac control registers */ 424 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 425 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 426 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 427 #define MAC_MCR_MAX_RX_1518 0x0 428 #define MAC_MCR_MAX_RX_1536 0x1 429 #define MAC_MCR_MAX_RX_1552 0x2 430 #define MAC_MCR_MAX_RX_2048 0x3 431 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 432 #define MAC_MCR_FORCE_MODE BIT(15) 433 #define MAC_MCR_TX_EN BIT(14) 434 #define MAC_MCR_RX_EN BIT(13) 435 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 436 #define MAC_MCR_BACKOFF_EN BIT(9) 437 #define MAC_MCR_BACKPR_EN BIT(8) 438 #define MAC_MCR_FORCE_RX_FC BIT(5) 439 #define MAC_MCR_FORCE_TX_FC BIT(4) 440 #define MAC_MCR_SPEED_1000 BIT(3) 441 #define MAC_MCR_SPEED_100 BIT(2) 442 #define MAC_MCR_FORCE_DPX BIT(1) 443 #define MAC_MCR_FORCE_LINK BIT(0) 444 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 445 446 /* Mac status registers */ 447 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 448 #define MAC_MSR_EEE1G BIT(7) 449 #define MAC_MSR_EEE100M BIT(6) 450 #define MAC_MSR_RX_FC BIT(5) 451 #define MAC_MSR_TX_FC BIT(4) 452 #define MAC_MSR_SPEED_1000 BIT(3) 453 #define MAC_MSR_SPEED_100 BIT(2) 454 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 455 #define MAC_MSR_DPX BIT(1) 456 #define MAC_MSR_LINK BIT(0) 457 458 /* TRGMII RXC control register */ 459 #define TRGMII_RCK_CTRL 0x10300 460 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 461 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 462 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 463 #define RXC_RST BIT(31) 464 #define RXC_DQSISEL BIT(30) 465 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 466 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 467 468 #define NUM_TRGMII_CTRL 5 469 470 /* TRGMII RXC control register */ 471 #define TRGMII_TCK_CTRL 0x10340 472 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 473 #define TXC_INV BIT(30) 474 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 475 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 476 477 /* TRGMII TX Drive Strength */ 478 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 479 #define TD_DM_DRVP(x) ((x) & 0xf) 480 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 481 482 /* TRGMII Interface mode register */ 483 #define INTF_MODE 0x10390 484 #define TRGMII_INTF_DIS BIT(0) 485 #define TRGMII_MODE BIT(1) 486 #define TRGMII_CENTRAL_ALIGNED BIT(2) 487 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 488 #define INTF_MODE_RGMII_10_100 0 489 490 /* GPIO port control registers for GMAC 2*/ 491 #define GPIO_OD33_CTRL8 0x4c0 492 #define GPIO_BIAS_CTRL 0xed0 493 #define GPIO_DRV_SEL10 0xf00 494 495 /* ethernet subsystem chip id register */ 496 #define ETHSYS_CHIPID0_3 0x0 497 #define ETHSYS_CHIPID4_7 0x4 498 #define MT7623_ETH 7623 499 #define MT7622_ETH 7622 500 #define MT7621_ETH 7621 501 502 /* ethernet system control register */ 503 #define ETHSYS_SYSCFG 0x10 504 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 505 506 /* ethernet subsystem config register */ 507 #define ETHSYS_SYSCFG0 0x14 508 #define SYSCFG0_GE_MASK 0x3 509 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 510 #define SYSCFG0_SGMII_MASK GENMASK(9, 7) 511 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 512 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 513 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 514 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 515 516 517 /* ethernet subsystem clock register */ 518 #define ETHSYS_CLKCFG0 0x2c 519 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 520 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 521 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 522 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 523 524 /* ethernet reset control register */ 525 #define ETHSYS_RSTCTRL 0x34 526 #define RSTCTRL_FE BIT(6) 527 #define RSTCTRL_WDMA0 BIT(24) 528 #define RSTCTRL_WDMA1 BIT(25) 529 #define RSTCTRL_WDMA2 BIT(26) 530 #define RSTCTRL_PPE0 BIT(31) 531 #define RSTCTRL_PPE0_V2 BIT(30) 532 #define RSTCTRL_PPE1 BIT(31) 533 #define RSTCTRL_PPE0_V3 BIT(29) 534 #define RSTCTRL_PPE1_V3 BIT(30) 535 #define RSTCTRL_PPE2 BIT(31) 536 #define RSTCTRL_ETH BIT(23) 537 538 /* ethernet reset check idle register */ 539 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 540 541 /* ethernet dma channel agent map */ 542 #define ETHSYS_DMA_AG_MAP 0x408 543 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 544 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 545 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 546 547 /* Infrasys subsystem config registers */ 548 #define INFRA_MISC2 0x70c 549 #define CO_QPHY_SEL BIT(0) 550 #define GEPHY_MAC_SEL BIT(1) 551 552 /* Top misc registers */ 553 #define USB_PHY_SWITCH_REG 0x218 554 #define QPHY_SEL_MASK GENMASK(1, 0) 555 #define SGMII_QPHY_SEL 0x2 556 557 /* MT7628/88 specific stuff */ 558 #define MT7628_PDMA_OFFSET 0x0800 559 #define MT7628_SDM_OFFSET 0x0c00 560 561 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 562 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 563 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 564 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 565 #define MT7628_PST_DTX_IDX0 BIT(0) 566 567 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 568 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 569 570 /* Counter / stat register */ 571 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 572 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 573 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 574 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 575 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 576 577 #define MTK_FE_CDM1_FSM 0x220 578 #define MTK_FE_CDM2_FSM 0x224 579 #define MTK_FE_CDM3_FSM 0x238 580 #define MTK_FE_CDM4_FSM 0x298 581 #define MTK_FE_CDM5_FSM 0x318 582 #define MTK_FE_CDM6_FSM 0x328 583 #define MTK_FE_GDM1_FSM 0x228 584 #define MTK_FE_GDM2_FSM 0x22C 585 586 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 587 588 struct mtk_rx_dma { 589 unsigned int rxd1; 590 unsigned int rxd2; 591 unsigned int rxd3; 592 unsigned int rxd4; 593 } __packed __aligned(4); 594 595 struct mtk_rx_dma_v2 { 596 unsigned int rxd1; 597 unsigned int rxd2; 598 unsigned int rxd3; 599 unsigned int rxd4; 600 unsigned int rxd5; 601 unsigned int rxd6; 602 unsigned int rxd7; 603 unsigned int rxd8; 604 } __packed __aligned(4); 605 606 struct mtk_tx_dma { 607 unsigned int txd1; 608 unsigned int txd2; 609 unsigned int txd3; 610 unsigned int txd4; 611 } __packed __aligned(4); 612 613 struct mtk_tx_dma_v2 { 614 unsigned int txd1; 615 unsigned int txd2; 616 unsigned int txd3; 617 unsigned int txd4; 618 unsigned int txd5; 619 unsigned int txd6; 620 unsigned int txd7; 621 unsigned int txd8; 622 } __packed __aligned(4); 623 624 struct mtk_eth; 625 struct mtk_mac; 626 627 struct mtk_xdp_stats { 628 u64 rx_xdp_redirect; 629 u64 rx_xdp_pass; 630 u64 rx_xdp_drop; 631 u64 rx_xdp_tx; 632 u64 rx_xdp_tx_errors; 633 u64 tx_xdp_xmit; 634 u64 tx_xdp_xmit_errors; 635 }; 636 637 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 638 * @stats_lock: make sure that stats operations are atomic 639 * @reg_offset: the status register offset of the SoC 640 * @syncp: the refcount 641 * 642 * All of the supported SoCs have hardware counters for traffic statistics. 643 * Whenever the status IRQ triggers we can read the latest stats from these 644 * counters and store them in this struct. 645 */ 646 struct mtk_hw_stats { 647 u64 tx_bytes; 648 u64 tx_packets; 649 u64 tx_skip; 650 u64 tx_collisions; 651 u64 rx_bytes; 652 u64 rx_packets; 653 u64 rx_overflow; 654 u64 rx_fcs_errors; 655 u64 rx_short_errors; 656 u64 rx_long_errors; 657 u64 rx_checksum_errors; 658 u64 rx_flow_control_packets; 659 660 struct mtk_xdp_stats xdp_stats; 661 662 spinlock_t stats_lock; 663 u32 reg_offset; 664 struct u64_stats_sync syncp; 665 }; 666 667 enum mtk_tx_flags { 668 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 669 * track how memory was allocated so that it can be freed properly. 670 */ 671 MTK_TX_FLAGS_SINGLE0 = 0x01, 672 MTK_TX_FLAGS_PAGE0 = 0x02, 673 }; 674 675 /* This enum allows us to identify how the clock is defined on the array of the 676 * clock in the order 677 */ 678 enum mtk_clks_map { 679 MTK_CLK_ETHIF, 680 MTK_CLK_SGMIITOP, 681 MTK_CLK_ESW, 682 MTK_CLK_GP0, 683 MTK_CLK_GP1, 684 MTK_CLK_GP2, 685 MTK_CLK_GP3, 686 MTK_CLK_XGP1, 687 MTK_CLK_XGP2, 688 MTK_CLK_XGP3, 689 MTK_CLK_CRYPTO, 690 MTK_CLK_FE, 691 MTK_CLK_TRGPLL, 692 MTK_CLK_SGMII_TX_250M, 693 MTK_CLK_SGMII_RX_250M, 694 MTK_CLK_SGMII_CDR_REF, 695 MTK_CLK_SGMII_CDR_FB, 696 MTK_CLK_SGMII2_TX_250M, 697 MTK_CLK_SGMII2_RX_250M, 698 MTK_CLK_SGMII2_CDR_REF, 699 MTK_CLK_SGMII2_CDR_FB, 700 MTK_CLK_SGMII_CK, 701 MTK_CLK_ETH2PLL, 702 MTK_CLK_WOCPU0, 703 MTK_CLK_WOCPU1, 704 MTK_CLK_NETSYS0, 705 MTK_CLK_NETSYS1, 706 MTK_CLK_ETHWARP_WOCPU2, 707 MTK_CLK_ETHWARP_WOCPU1, 708 MTK_CLK_ETHWARP_WOCPU0, 709 MTK_CLK_TOP_USXGMII_SBUS_0_SEL, 710 MTK_CLK_TOP_USXGMII_SBUS_1_SEL, 711 MTK_CLK_TOP_SGM_0_SEL, 712 MTK_CLK_TOP_SGM_1_SEL, 713 MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, 714 MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, 715 MTK_CLK_TOP_ETH_GMII_SEL, 716 MTK_CLK_TOP_ETH_REFCK_50M_SEL, 717 MTK_CLK_TOP_ETH_SYS_200M_SEL, 718 MTK_CLK_TOP_ETH_SYS_SEL, 719 MTK_CLK_TOP_ETH_XGMII_SEL, 720 MTK_CLK_TOP_ETH_MII_SEL, 721 MTK_CLK_TOP_NETSYS_SEL, 722 MTK_CLK_TOP_NETSYS_500M_SEL, 723 MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 724 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 725 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 726 MTK_CLK_TOP_NETSYS_WARP_SEL, 727 MTK_CLK_MAX 728 }; 729 730 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 731 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 732 BIT_ULL(MTK_CLK_TRGPLL)) 733 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 734 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 735 BIT_ULL(MTK_CLK_GP2) | \ 736 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 737 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 738 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 739 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 740 BIT_ULL(MTK_CLK_SGMII_CK) | \ 741 BIT_ULL(MTK_CLK_ETH2PLL)) 742 #define MT7621_CLKS_BITMAP (0) 743 #define MT7628_CLKS_BITMAP (0) 744 #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 745 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 746 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 747 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 748 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 749 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 750 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 751 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 752 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 753 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 754 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 755 BIT_ULL(MTK_CLK_SGMII_CK) | \ 756 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 757 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 758 BIT_ULL(MTK_CLK_GP1) | \ 759 BIT_ULL(MTK_CLK_WOCPU0) | \ 760 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 761 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 762 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 763 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 764 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 765 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 766 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 767 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 768 BIT_ULL(MTK_CLK_SGMII_CK)) 769 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 770 BIT_ULL(MTK_CLK_GP1) | \ 771 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 772 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 773 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 774 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 775 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 776 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 777 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 778 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 779 BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 780 #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 781 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 782 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 783 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 784 BIT_ULL(MTK_CLK_CRYPTO) | \ 785 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 786 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 787 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 788 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 789 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 790 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 791 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 792 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ 793 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ 794 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ 795 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ 796 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ 797 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ 798 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 799 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 800 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 801 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 802 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 803 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 804 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 805 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 806 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 807 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 808 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 809 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 810 811 enum mtk_dev_state { 812 MTK_HW_INIT, 813 MTK_RESETTING 814 }; 815 816 /* PSE Port Definition */ 817 enum mtk_pse_port { 818 PSE_ADMA_PORT = 0, 819 PSE_GDM1_PORT, 820 PSE_GDM2_PORT, 821 PSE_PPE0_PORT, 822 PSE_PPE1_PORT, 823 PSE_QDMA_TX_PORT, 824 PSE_QDMA_RX_PORT, 825 PSE_DROP_PORT, 826 PSE_WDMA0_PORT, 827 PSE_WDMA1_PORT, 828 PSE_TDMA_PORT, 829 PSE_NONE_PORT, 830 PSE_PPE2_PORT, 831 PSE_WDMA2_PORT, 832 PSE_EIP197_PORT, 833 PSE_GDM3_PORT, 834 PSE_PORT_MAX 835 }; 836 837 /* GMAC Identifier */ 838 enum mtk_gmac_id { 839 MTK_GMAC1_ID = 0, 840 MTK_GMAC2_ID, 841 MTK_GMAC3_ID, 842 MTK_GMAC_ID_MAX 843 }; 844 845 enum mtk_tx_buf_type { 846 MTK_TYPE_SKB, 847 MTK_TYPE_XDP_TX, 848 MTK_TYPE_XDP_NDO, 849 }; 850 851 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 852 * by the TX descriptor s 853 * @skb: The SKB pointer of the packet being sent 854 * @dma_addr0: The base addr of the first segment 855 * @dma_len0: The length of the first segment 856 * @dma_addr1: The base addr of the second segment 857 * @dma_len1: The length of the second segment 858 */ 859 struct mtk_tx_buf { 860 enum mtk_tx_buf_type type; 861 void *data; 862 863 u16 mac_id; 864 u16 flags; 865 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 866 DEFINE_DMA_UNMAP_LEN(dma_len0); 867 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 868 DEFINE_DMA_UNMAP_LEN(dma_len1); 869 }; 870 871 /* struct mtk_tx_ring - This struct holds info describing a TX ring 872 * @dma: The descriptor ring 873 * @buf: The memory pointed at by the ring 874 * @phys: The physical addr of tx_buf 875 * @next_free: Pointer to the next free descriptor 876 * @last_free: Pointer to the last free descriptor 877 * @last_free_ptr: Hardware pointer value of the last free descriptor 878 * @thresh: The threshold of minimum amount of free descriptors 879 * @free_count: QDMA uses a linked list. Track how many free descriptors 880 * are present 881 */ 882 struct mtk_tx_ring { 883 void *dma; 884 struct mtk_tx_buf *buf; 885 dma_addr_t phys; 886 struct mtk_tx_dma *next_free; 887 struct mtk_tx_dma *last_free; 888 u32 last_free_ptr; 889 u16 thresh; 890 atomic_t free_count; 891 int dma_size; 892 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 893 dma_addr_t phys_pdma; 894 int cpu_idx; 895 }; 896 897 /* PDMA rx ring mode */ 898 enum mtk_rx_flags { 899 MTK_RX_FLAGS_NORMAL = 0, 900 MTK_RX_FLAGS_HWLRO, 901 MTK_RX_FLAGS_QDMA, 902 }; 903 904 /* struct mtk_rx_ring - This struct holds info describing a RX ring 905 * @dma: The descriptor ring 906 * @data: The memory pointed at by the ring 907 * @phys: The physical addr of rx_buf 908 * @frag_size: How big can each fragment be 909 * @buf_size: The size of each packet buffer 910 * @calc_idx: The current head of ring 911 */ 912 struct mtk_rx_ring { 913 void *dma; 914 u8 **data; 915 dma_addr_t phys; 916 u16 frag_size; 917 u16 buf_size; 918 u16 dma_size; 919 bool calc_idx_update; 920 u16 calc_idx; 921 u32 crx_idx_reg; 922 /* page_pool */ 923 struct page_pool *page_pool; 924 struct xdp_rxq_info xdp_q; 925 }; 926 927 enum mkt_eth_capabilities { 928 MTK_RGMII_BIT = 0, 929 MTK_TRGMII_BIT, 930 MTK_SGMII_BIT, 931 MTK_ESW_BIT, 932 MTK_GEPHY_BIT, 933 MTK_MUX_BIT, 934 MTK_INFRA_BIT, 935 MTK_SHARED_SGMII_BIT, 936 MTK_HWLRO_BIT, 937 MTK_SHARED_INT_BIT, 938 MTK_TRGMII_MT7621_CLK_BIT, 939 MTK_QDMA_BIT, 940 MTK_SOC_MT7628_BIT, 941 MTK_RSTCTRL_PPE1_BIT, 942 MTK_RSTCTRL_PPE2_BIT, 943 MTK_U3_COPHY_V2_BIT, 944 MTK_SRAM_BIT, 945 946 /* MUX BITS*/ 947 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 948 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 949 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 950 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 951 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 952 953 /* PATH BITS */ 954 MTK_ETH_PATH_GMAC1_RGMII_BIT, 955 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 956 MTK_ETH_PATH_GMAC1_SGMII_BIT, 957 MTK_ETH_PATH_GMAC2_RGMII_BIT, 958 MTK_ETH_PATH_GMAC2_SGMII_BIT, 959 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 960 MTK_ETH_PATH_GDM1_ESW_BIT, 961 }; 962 963 /* Supported hardware group on SoCs */ 964 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 965 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 966 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 967 #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 968 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 969 #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 970 #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 971 #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 972 #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 973 #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 974 #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 975 #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 976 #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 977 #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 978 #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) 979 #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 980 #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT) 981 982 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 983 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 984 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 985 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 986 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 987 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 988 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 989 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 990 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 991 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 992 993 /* Supported path present on SoCs */ 994 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 995 #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 996 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 997 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 998 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 999 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 1000 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 1001 1002 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 1003 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 1004 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 1005 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 1006 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 1007 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 1008 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 1009 1010 /* MUXes present on SoCs */ 1011 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 1012 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 1013 1014 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 1015 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 1016 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 1017 1018 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 1019 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 1020 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 1021 1022 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 1023 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1024 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 1025 MTK_SHARED_SGMII) 1026 1027 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 1028 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 1029 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 1030 1031 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 1032 1033 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 1034 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 1035 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 1036 1037 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 1038 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 1039 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1040 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 1041 1042 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 1043 MTK_QDMA) 1044 1045 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 1046 1047 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1048 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1049 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 1050 MTK_MUX_U3_GMAC2_TO_QPHY | \ 1051 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 1052 1053 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1054 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1055 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1056 MTK_RSTCTRL_PPE1 | MTK_SRAM) 1057 1058 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1059 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1060 MTK_RSTCTRL_PPE1 | MTK_SRAM) 1061 1062 #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ 1063 MTK_RSTCTRL_PPE2 | MTK_SRAM) 1064 1065 struct mtk_tx_dma_desc_info { 1066 dma_addr_t addr; 1067 u32 size; 1068 u16 vlan_tci; 1069 u16 qid; 1070 u8 gso:1; 1071 u8 csum:1; 1072 u8 vlan:1; 1073 u8 first:1; 1074 u8 last:1; 1075 }; 1076 1077 struct mtk_reg_map { 1078 u32 tx_irq_mask; 1079 u32 tx_irq_status; 1080 struct { 1081 u32 rx_ptr; /* rx base pointer */ 1082 u32 rx_cnt_cfg; /* rx max count configuration */ 1083 u32 pcrx_ptr; /* rx cpu pointer */ 1084 u32 glo_cfg; /* global configuration */ 1085 u32 rst_idx; /* reset index */ 1086 u32 delay_irq; /* delay interrupt */ 1087 u32 irq_status; /* interrupt status */ 1088 u32 irq_mask; /* interrupt mask */ 1089 u32 adma_rx_dbg0; 1090 u32 int_grp; 1091 } pdma; 1092 struct { 1093 u32 qtx_cfg; /* tx queue configuration */ 1094 u32 qtx_sch; /* tx queue scheduler configuration */ 1095 u32 rx_ptr; /* rx base pointer */ 1096 u32 rx_cnt_cfg; /* rx max count configuration */ 1097 u32 qcrx_ptr; /* rx cpu pointer */ 1098 u32 glo_cfg; /* global configuration */ 1099 u32 rst_idx; /* reset index */ 1100 u32 delay_irq; /* delay interrupt */ 1101 u32 fc_th; /* flow control */ 1102 u32 int_grp; 1103 u32 hred; /* interrupt mask */ 1104 u32 ctx_ptr; /* tx acquire cpu pointer */ 1105 u32 dtx_ptr; /* tx acquire dma pointer */ 1106 u32 crx_ptr; /* tx release cpu pointer */ 1107 u32 drx_ptr; /* tx release dma pointer */ 1108 u32 fq_head; /* fq head pointer */ 1109 u32 fq_tail; /* fq tail pointer */ 1110 u32 fq_count; /* fq free page count */ 1111 u32 fq_blen; /* fq free page buffer length */ 1112 u32 tx_sch_rate; /* tx scheduler rate control registers */ 1113 } qdma; 1114 u32 gdm1_cnt; 1115 u32 gdma_to_ppe; 1116 u32 ppe_base; 1117 u32 wdma_base[2]; 1118 u32 pse_iq_sta; 1119 u32 pse_oq_sta; 1120 }; 1121 1122 /* struct mtk_eth_data - This is the structure holding all differences 1123 * among various plaforms 1124 * @reg_map Soc register map. 1125 * @ana_rgc3: The offset for register ANA_RGC3 related to 1126 * sgmiisys syscon 1127 * @caps Flags shown the extra capability for the SoC 1128 * @hw_features Flags shown HW features 1129 * @required_clks Flags shown the bitmap for required clocks on 1130 * the target SoC 1131 * @required_pctl A bool value to show whether the SoC requires 1132 * the extra setup for those pins used by GMAC. 1133 * @hash_offset Flow table hash offset. 1134 * @version SoC version. 1135 * @foe_entry_size Foe table entry size. 1136 * @has_accounting Bool indicating support for accounting of 1137 * offloaded flows. 1138 * @txd_size Tx DMA descriptor size. 1139 * @rxd_size Rx DMA descriptor size. 1140 * @rx_irq_done_mask Rx irq done register mask. 1141 * @rx_dma_l4_valid Rx DMA valid register mask. 1142 * @dma_max_len Max DMA tx/rx buffer length. 1143 * @dma_len_offset Tx/Rx DMA length field offset. 1144 */ 1145 struct mtk_soc_data { 1146 const struct mtk_reg_map *reg_map; 1147 u32 ana_rgc3; 1148 u64 caps; 1149 u64 required_clks; 1150 bool required_pctl; 1151 u8 offload_version; 1152 u8 hash_offset; 1153 u8 version; 1154 u16 foe_entry_size; 1155 netdev_features_t hw_features; 1156 bool has_accounting; 1157 bool disable_pll_modes; 1158 struct { 1159 u32 txd_size; 1160 u32 rxd_size; 1161 u32 rx_irq_done_mask; 1162 u32 rx_dma_l4_valid; 1163 u32 dma_max_len; 1164 u32 dma_len_offset; 1165 } txrx; 1166 }; 1167 1168 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1169 1170 /* currently no SoC has more than 3 macs */ 1171 #define MTK_MAX_DEVS 3 1172 1173 /* struct mtk_eth - This is the main datasructure for holding the state 1174 * of the driver 1175 * @dev: The device pointer 1176 * @dev: The device pointer used for dma mapping/alloc 1177 * @base: The mapped register i/o base 1178 * @page_lock: Make sure that register operations are atomic 1179 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1180 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1181 * @dim_lock: Make sure that Net DIM operations are atomic 1182 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1183 * dummy for NAPI to work 1184 * @netdev: The netdev instances 1185 * @mac: Each netdev is linked to a physical MAC 1186 * @irq: The IRQ that we are using 1187 * @msg_enable: Ethtool msg level 1188 * @ethsys: The register map pointing at the range used to setup 1189 * MII modes 1190 * @infra: The register map pointing at the range used to setup 1191 * SGMII and GePHY path 1192 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1193 * @pctl: The register map pointing at the range used to setup 1194 * GMAC port drive/slew values 1195 * @dma_refcnt: track how many netdevs are using the DMA engine 1196 * @tx_ring: Pointer to the memory holding info about the TX ring 1197 * @rx_ring: Pointer to the memory holding info about the RX ring 1198 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1199 * @tx_napi: The TX NAPI struct 1200 * @rx_napi: The RX NAPI struct 1201 * @rx_events: Net DIM RX event counter 1202 * @rx_packets: Net DIM RX packet counter 1203 * @rx_bytes: Net DIM RX byte counter 1204 * @rx_dim: Net DIM RX context 1205 * @tx_events: Net DIM TX event counter 1206 * @tx_packets: Net DIM TX packet counter 1207 * @tx_bytes: Net DIM TX byte counter 1208 * @tx_dim: Net DIM TX context 1209 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1210 * @phy_scratch_ring: physical address of scratch_ring 1211 * @scratch_head: The scratch memory that scratch_ring points to. 1212 * @clks: clock array for all clocks required 1213 * @mii_bus: If there is a bus we need to create an instance for it 1214 * @pending_work: The workqueue used to reset the dma ring 1215 * @state: Initialization and runtime state of the device 1216 * @soc: Holding specific data among vaious SoCs 1217 */ 1218 1219 struct mtk_eth { 1220 struct device *dev; 1221 struct device *dma_dev; 1222 void __iomem *base; 1223 void *sram_base; 1224 spinlock_t page_lock; 1225 spinlock_t tx_irq_lock; 1226 spinlock_t rx_irq_lock; 1227 struct net_device dummy_dev; 1228 struct net_device *netdev[MTK_MAX_DEVS]; 1229 struct mtk_mac *mac[MTK_MAX_DEVS]; 1230 int irq[3]; 1231 u32 msg_enable; 1232 unsigned long sysclk; 1233 struct regmap *ethsys; 1234 struct regmap *infra; 1235 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1236 struct regmap *pctl; 1237 bool hwlro; 1238 refcount_t dma_refcnt; 1239 struct mtk_tx_ring tx_ring; 1240 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1241 struct mtk_rx_ring rx_ring_qdma; 1242 struct napi_struct tx_napi; 1243 struct napi_struct rx_napi; 1244 void *scratch_ring; 1245 dma_addr_t phy_scratch_ring; 1246 void *scratch_head; 1247 struct clk *clks[MTK_CLK_MAX]; 1248 1249 struct mii_bus *mii_bus; 1250 struct work_struct pending_work; 1251 unsigned long state; 1252 1253 const struct mtk_soc_data *soc; 1254 1255 spinlock_t dim_lock; 1256 1257 u32 rx_events; 1258 u32 rx_packets; 1259 u32 rx_bytes; 1260 struct dim rx_dim; 1261 1262 u32 tx_events; 1263 u32 tx_packets; 1264 u32 tx_bytes; 1265 struct dim tx_dim; 1266 1267 int ip_align; 1268 1269 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1270 1271 struct mtk_ppe *ppe[2]; 1272 struct rhashtable flow_table; 1273 1274 struct bpf_prog __rcu *prog; 1275 1276 struct { 1277 struct delayed_work monitor_work; 1278 u32 wdidx; 1279 u8 wdma_hang_count; 1280 u8 qdma_hang_count; 1281 u8 adma_hang_count; 1282 } reset; 1283 }; 1284 1285 /* struct mtk_mac - the structure that holds the info about the MACs of the 1286 * SoC 1287 * @id: The number of the MAC 1288 * @interface: Interface mode kept for detecting change in hw settings 1289 * @of_node: Our devicetree node 1290 * @hw: Backpointer to our main datastruture 1291 * @hw_stats: Packet statistics counter 1292 */ 1293 struct mtk_mac { 1294 int id; 1295 phy_interface_t interface; 1296 int speed; 1297 struct device_node *of_node; 1298 struct phylink *phylink; 1299 struct phylink_config phylink_config; 1300 struct mtk_eth *hw; 1301 struct mtk_hw_stats *hw_stats; 1302 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1303 int hwlro_ip_cnt; 1304 unsigned int syscfg0; 1305 struct notifier_block device_notifier; 1306 }; 1307 1308 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1309 extern const struct of_device_id of_mtk_match[]; 1310 1311 static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1312 { 1313 return eth->soc->version == 1; 1314 } 1315 1316 static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1317 { 1318 return eth->soc->version > 1; 1319 } 1320 1321 static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 1322 { 1323 return eth->soc->version > 2; 1324 } 1325 1326 static inline struct mtk_foe_entry * 1327 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1328 { 1329 const struct mtk_soc_data *soc = ppe->eth->soc; 1330 1331 return ppe->foe_table + hash * soc->foe_entry_size; 1332 } 1333 1334 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1335 { 1336 if (mtk_is_netsys_v2_or_greater(eth)) 1337 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1338 1339 return MTK_FOE_IB1_BIND_TIMESTAMP; 1340 } 1341 1342 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1343 { 1344 if (mtk_is_netsys_v2_or_greater(eth)) 1345 return MTK_FOE_IB1_BIND_PPPOE_V2; 1346 1347 return MTK_FOE_IB1_BIND_PPPOE; 1348 } 1349 1350 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1351 { 1352 if (mtk_is_netsys_v2_or_greater(eth)) 1353 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1354 1355 return MTK_FOE_IB1_BIND_VLAN_TAG; 1356 } 1357 1358 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1359 { 1360 if (mtk_is_netsys_v2_or_greater(eth)) 1361 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1362 1363 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1364 } 1365 1366 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1367 { 1368 if (mtk_is_netsys_v2_or_greater(eth)) 1369 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1370 1371 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1372 } 1373 1374 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1375 { 1376 if (mtk_is_netsys_v2_or_greater(eth)) 1377 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1378 1379 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1380 } 1381 1382 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1383 { 1384 if (mtk_is_netsys_v2_or_greater(eth)) 1385 return MTK_FOE_IB1_PACKET_TYPE_V2; 1386 1387 return MTK_FOE_IB1_PACKET_TYPE; 1388 } 1389 1390 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1391 { 1392 if (mtk_is_netsys_v2_or_greater(eth)) 1393 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1394 1395 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1396 } 1397 1398 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1399 { 1400 if (mtk_is_netsys_v2_or_greater(eth)) 1401 return MTK_FOE_IB2_MULTICAST_V2; 1402 1403 return MTK_FOE_IB2_MULTICAST; 1404 } 1405 1406 /* read the hardware status register */ 1407 void mtk_stats_update_mac(struct mtk_mac *mac); 1408 1409 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1410 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1411 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1412 1413 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1414 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1415 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1416 1417 int mtk_eth_offload_init(struct mtk_eth *eth); 1418 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1419 void *type_data); 1420 int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 1421 int ppe_index); 1422 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1423 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1424 1425 1426 #endif /* MTK_ETH_H */ 1427