1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Texas Instruments DS90UB953 video serializer
4 *
5 * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net>
6 *
7 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
8 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/fwnode.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c-atr.h>
17 #include <linux/i2c.h>
18 #include <linux/kernel.h>
19 #include <linux/math64.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/rational.h>
23 #include <linux/regmap.h>
24
25 #include <media/i2c/ds90ub9xx.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
31
32 #define UB953_PAD_SINK 0
33 #define UB953_PAD_SOURCE 1
34
35 #define UB953_NUM_GPIOS 4
36
37 #define UB953_DEFAULT_CLKOUT_RATE 25000000UL
38
39 #define UB953_REG_RESET_CTL 0x01
40 #define UB953_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
41 #define UB953_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
42
43 #define UB953_REG_GENERAL_CFG 0x02
44 #define UB953_REG_GENERAL_CFG_CONT_CLK BIT(6)
45 #define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT 4
46 #define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK GENMASK(5, 4)
47 #define UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE BIT(1)
48 #define UB953_REG_GENERAL_CFG_I2C_STRAP_MODE BIT(0)
49
50 #define UB953_REG_MODE_SEL 0x03
51 #define UB953_REG_MODE_SEL_MODE_DONE BIT(3)
52 #define UB953_REG_MODE_SEL_MODE_OVERRIDE BIT(4)
53 #define UB953_REG_MODE_SEL_MODE_MASK GENMASK(2, 0)
54
55 #define UB953_REG_CLKOUT_CTRL0 0x06
56 #define UB953_REG_CLKOUT_CTRL1 0x07
57
58 #define UB953_REG_SCL_HIGH_TIME 0x0b
59 #define UB953_REG_SCL_LOW_TIME 0x0c
60
61 #define UB953_REG_LOCAL_GPIO_DATA 0x0d
62 #define UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(n) BIT(4 + (n))
63 #define UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(n) BIT(0 + (n))
64
65 #define UB953_REG_GPIO_INPUT_CTRL 0x0e
66 #define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n) BIT(4 + (n))
67 #define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n) BIT(0 + (n))
68
69 #define UB953_REG_REV_MASK_ID 0x50
70 #define UB953_REG_GENERAL_STATUS 0x52
71
72 #define UB953_REG_GPIO_PIN_STS 0x53
73 #define UB953_REG_GPIO_PIN_STS_GPIO_STS(n) BIT(0 + (n))
74
75 #define UB953_REG_BIST_ERR_CNT 0x54
76 #define UB953_REG_CRC_ERR_CNT1 0x55
77 #define UB953_REG_CRC_ERR_CNT2 0x56
78
79 #define UB953_REG_CSI_ERR_CNT 0x5c
80 #define UB953_REG_CSI_ERR_STATUS 0x5d
81 #define UB953_REG_CSI_ERR_DLANE01 0x5e
82 #define UB953_REG_CSI_ERR_DLANE23 0x5f
83 #define UB953_REG_CSI_ERR_CLK_LANE 0x60
84 #define UB953_REG_CSI_PKT_HDR_VC_ID 0x61
85 #define UB953_REG_PKT_HDR_WC_LSB 0x62
86 #define UB953_REG_PKT_HDR_WC_MSB 0x63
87 #define UB953_REG_CSI_ECC 0x64
88
89 #define UB953_REG_IND_ACC_CTL 0xb0
90 #define UB953_REG_IND_ACC_ADDR 0xb1
91 #define UB953_REG_IND_ACC_DATA 0xb2
92
93 #define UB953_REG_FPD3_RX_ID(n) (0xf0 + (n))
94 #define UB953_REG_FPD3_RX_ID_LEN 6
95
96 /* Indirect register blocks */
97 #define UB953_IND_TARGET_PAT_GEN 0x00
98 #define UB953_IND_TARGET_FPD3_TX 0x01
99 #define UB953_IND_TARGET_DIE_ID 0x02
100
101 #define UB953_IND_PGEN_CTL 0x01
102 #define UB953_IND_PGEN_CTL_PGEN_ENABLE BIT(0)
103 #define UB953_IND_PGEN_CFG 0x02
104 #define UB953_IND_PGEN_CSI_DI 0x03
105 #define UB953_IND_PGEN_LINE_SIZE1 0x04
106 #define UB953_IND_PGEN_LINE_SIZE0 0x05
107 #define UB953_IND_PGEN_BAR_SIZE1 0x06
108 #define UB953_IND_PGEN_BAR_SIZE0 0x07
109 #define UB953_IND_PGEN_ACT_LPF1 0x08
110 #define UB953_IND_PGEN_ACT_LPF0 0x09
111 #define UB953_IND_PGEN_TOT_LPF1 0x0a
112 #define UB953_IND_PGEN_TOT_LPF0 0x0b
113 #define UB953_IND_PGEN_LINE_PD1 0x0c
114 #define UB953_IND_PGEN_LINE_PD0 0x0d
115 #define UB953_IND_PGEN_VBP 0x0e
116 #define UB953_IND_PGEN_VFP 0x0f
117 #define UB953_IND_PGEN_COLOR(n) (0x10 + (n)) /* n <= 15 */
118
119 /* Note: Only sync mode supported for now */
120 enum ub953_mode {
121 /* FPD-Link III CSI-2 synchronous mode */
122 UB953_MODE_SYNC,
123 /* FPD-Link III CSI-2 non-synchronous mode, external ref clock */
124 UB953_MODE_NONSYNC_EXT,
125 /* FPD-Link III CSI-2 non-synchronous mode, internal ref clock */
126 UB953_MODE_NONSYNC_INT,
127 /* FPD-Link III DVP mode */
128 UB953_MODE_DVP,
129 };
130
131 struct ub953_hw_data {
132 const char *model;
133 bool is_ub971;
134 };
135
136 struct ub953_clkout_data {
137 u32 hs_div;
138 u32 m;
139 u32 n;
140 unsigned long rate;
141 };
142
143 struct ub953_data {
144 const struct ub953_hw_data *hw_data;
145
146 struct i2c_client *client;
147 struct regmap *regmap;
148 struct clk *clkin;
149
150 u32 num_data_lanes;
151 bool non_continous_clk;
152
153 struct gpio_chip gpio_chip;
154
155 struct v4l2_subdev sd;
156 struct media_pad pads[2];
157
158 struct v4l2_async_notifier notifier;
159
160 struct v4l2_subdev *source_sd;
161 u16 source_sd_pad;
162
163 u64 enabled_source_streams;
164
165 /* lock for register access */
166 struct mutex reg_lock;
167
168 u8 current_indirect_target;
169
170 struct clk_hw clkout_clk_hw;
171
172 enum ub953_mode mode;
173
174 const struct ds90ub9xx_platform_data *plat_data;
175 };
176
sd_to_ub953(struct v4l2_subdev * sd)177 static inline struct ub953_data *sd_to_ub953(struct v4l2_subdev *sd)
178 {
179 return container_of(sd, struct ub953_data, sd);
180 }
181
182 /*
183 * HW Access
184 */
185
ub953_read(struct ub953_data * priv,u8 reg,u8 * val)186 static int ub953_read(struct ub953_data *priv, u8 reg, u8 *val)
187 {
188 unsigned int v;
189 int ret;
190
191 mutex_lock(&priv->reg_lock);
192
193 ret = regmap_read(priv->regmap, reg, &v);
194 if (ret) {
195 dev_err(&priv->client->dev, "Cannot read register 0x%02x: %d\n",
196 reg, ret);
197 goto out_unlock;
198 }
199
200 *val = v;
201
202 out_unlock:
203 mutex_unlock(&priv->reg_lock);
204
205 return ret;
206 }
207
ub953_write(struct ub953_data * priv,u8 reg,u8 val)208 static int ub953_write(struct ub953_data *priv, u8 reg, u8 val)
209 {
210 int ret;
211
212 mutex_lock(&priv->reg_lock);
213
214 ret = regmap_write(priv->regmap, reg, val);
215 if (ret)
216 dev_err(&priv->client->dev,
217 "Cannot write register 0x%02x: %d\n", reg, ret);
218
219 mutex_unlock(&priv->reg_lock);
220
221 return ret;
222 }
223
ub953_select_ind_reg_block(struct ub953_data * priv,u8 block)224 static int ub953_select_ind_reg_block(struct ub953_data *priv, u8 block)
225 {
226 struct device *dev = &priv->client->dev;
227 int ret;
228
229 if (priv->current_indirect_target == block)
230 return 0;
231
232 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_CTL, block << 2);
233 if (ret) {
234 dev_err(dev, "%s: cannot select indirect target %u (%d)\n",
235 __func__, block, ret);
236 return ret;
237 }
238
239 priv->current_indirect_target = block;
240
241 return 0;
242 }
243
244 __maybe_unused
ub953_read_ind(struct ub953_data * priv,u8 block,u8 reg,u8 * val)245 static int ub953_read_ind(struct ub953_data *priv, u8 block, u8 reg, u8 *val)
246 {
247 unsigned int v;
248 int ret;
249
250 mutex_lock(&priv->reg_lock);
251
252 ret = ub953_select_ind_reg_block(priv, block);
253 if (ret)
254 goto out_unlock;
255
256 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg);
257 if (ret) {
258 dev_err(&priv->client->dev,
259 "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n",
260 block, reg, ret);
261 goto out_unlock;
262 }
263
264 ret = regmap_read(priv->regmap, UB953_REG_IND_ACC_DATA, &v);
265 if (ret) {
266 dev_err(&priv->client->dev,
267 "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n",
268 block, reg, ret);
269 goto out_unlock;
270 }
271
272 *val = v;
273
274 out_unlock:
275 mutex_unlock(&priv->reg_lock);
276
277 return ret;
278 }
279
280 __maybe_unused
ub953_write_ind(struct ub953_data * priv,u8 block,u8 reg,u8 val)281 static int ub953_write_ind(struct ub953_data *priv, u8 block, u8 reg, u8 val)
282 {
283 int ret;
284
285 mutex_lock(&priv->reg_lock);
286
287 ret = ub953_select_ind_reg_block(priv, block);
288 if (ret)
289 goto out_unlock;
290
291 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_ADDR, reg);
292 if (ret) {
293 dev_err(&priv->client->dev,
294 "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n",
295 block, reg, ret);
296 goto out_unlock;
297 }
298
299 ret = regmap_write(priv->regmap, UB953_REG_IND_ACC_DATA, val);
300 if (ret) {
301 dev_err(&priv->client->dev,
302 "Write to IND_ACC_DATA failed when writing %u:%x02x\n: %d\n",
303 block, reg, ret);
304 }
305
306 out_unlock:
307 mutex_unlock(&priv->reg_lock);
308
309 return ret;
310 }
311
312 /*
313 * GPIO chip
314 */
ub953_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)315 static int ub953_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
316 {
317 struct ub953_data *priv = gpiochip_get_data(gc);
318 int ret;
319 u8 v;
320
321 ret = ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &v);
322 if (ret)
323 return ret;
324
325 if (v & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset))
326 return GPIO_LINE_DIRECTION_IN;
327 else
328 return GPIO_LINE_DIRECTION_OUT;
329 }
330
ub953_gpio_direction_in(struct gpio_chip * gc,unsigned int offset)331 static int ub953_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
332 {
333 struct ub953_data *priv = gpiochip_get_data(gc);
334
335 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL,
336 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) |
337 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset),
338 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset));
339 }
340
ub953_gpio_direction_out(struct gpio_chip * gc,unsigned int offset,int value)341 static int ub953_gpio_direction_out(struct gpio_chip *gc, unsigned int offset,
342 int value)
343 {
344 struct ub953_data *priv = gpiochip_get_data(gc);
345 int ret;
346
347 ret = regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA,
348 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset),
349 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) :
350 0);
351
352 if (ret)
353 return ret;
354
355 return regmap_update_bits(priv->regmap, UB953_REG_GPIO_INPUT_CTRL,
356 UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset) |
357 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset),
358 UB953_REG_GPIO_INPUT_CTRL_OUT_EN(offset));
359 }
360
ub953_gpio_get(struct gpio_chip * gc,unsigned int offset)361 static int ub953_gpio_get(struct gpio_chip *gc, unsigned int offset)
362 {
363 struct ub953_data *priv = gpiochip_get_data(gc);
364 int ret;
365 u8 v;
366
367 ret = ub953_read(priv, UB953_REG_GPIO_PIN_STS, &v);
368 if (ret)
369 return ret;
370
371 return !!(v & UB953_REG_GPIO_PIN_STS_GPIO_STS(offset));
372 }
373
ub953_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)374 static void ub953_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
375 {
376 struct ub953_data *priv = gpiochip_get_data(gc);
377
378 regmap_update_bits(priv->regmap, UB953_REG_LOCAL_GPIO_DATA,
379 UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset),
380 value ? UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(offset) :
381 0);
382 }
383
ub953_gpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)384 static int ub953_gpio_of_xlate(struct gpio_chip *gc,
385 const struct of_phandle_args *gpiospec,
386 u32 *flags)
387 {
388 if (flags)
389 *flags = gpiospec->args[1];
390
391 return gpiospec->args[0];
392 }
393
ub953_gpiochip_probe(struct ub953_data * priv)394 static int ub953_gpiochip_probe(struct ub953_data *priv)
395 {
396 struct device *dev = &priv->client->dev;
397 struct gpio_chip *gc = &priv->gpio_chip;
398 int ret;
399
400 /* Set all GPIOs to local input mode */
401 ret = ub953_write(priv, UB953_REG_LOCAL_GPIO_DATA, 0);
402 if (ret)
403 return ret;
404
405 ret = ub953_write(priv, UB953_REG_GPIO_INPUT_CTRL, 0xf);
406 if (ret)
407 return ret;
408
409 gc->label = dev_name(dev);
410 gc->parent = dev;
411 gc->owner = THIS_MODULE;
412 gc->base = -1;
413 gc->can_sleep = true;
414 gc->ngpio = UB953_NUM_GPIOS;
415 gc->get_direction = ub953_gpio_get_direction;
416 gc->direction_input = ub953_gpio_direction_in;
417 gc->direction_output = ub953_gpio_direction_out;
418 gc->get = ub953_gpio_get;
419 gc->set = ub953_gpio_set;
420 gc->of_xlate = ub953_gpio_of_xlate;
421 gc->of_gpio_n_cells = 2;
422
423 ret = gpiochip_add_data(gc, priv);
424 if (ret) {
425 dev_err(dev, "Failed to add GPIOs: %d\n", ret);
426 return ret;
427 }
428
429 return 0;
430 }
431
ub953_gpiochip_remove(struct ub953_data * priv)432 static void ub953_gpiochip_remove(struct ub953_data *priv)
433 {
434 gpiochip_remove(&priv->gpio_chip);
435 }
436
437 /*
438 * V4L2
439 */
440
_ub953_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_krouting * routing)441 static int _ub953_set_routing(struct v4l2_subdev *sd,
442 struct v4l2_subdev_state *state,
443 struct v4l2_subdev_krouting *routing)
444 {
445 static const struct v4l2_mbus_framefmt format = {
446 .width = 640,
447 .height = 480,
448 .code = MEDIA_BUS_FMT_UYVY8_1X16,
449 .field = V4L2_FIELD_NONE,
450 .colorspace = V4L2_COLORSPACE_SRGB,
451 .ycbcr_enc = V4L2_YCBCR_ENC_601,
452 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
453 .xfer_func = V4L2_XFER_FUNC_SRGB,
454 };
455 int ret;
456
457 /*
458 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
459 * frame desc is made dynamically allocated.
460 */
461
462 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
463 return -EINVAL;
464
465 ret = v4l2_subdev_routing_validate(sd, routing,
466 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
467 if (ret)
468 return ret;
469
470 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
471 if (ret)
472 return ret;
473
474 return 0;
475 }
476
ub953_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,enum v4l2_subdev_format_whence which,struct v4l2_subdev_krouting * routing)477 static int ub953_set_routing(struct v4l2_subdev *sd,
478 struct v4l2_subdev_state *state,
479 enum v4l2_subdev_format_whence which,
480 struct v4l2_subdev_krouting *routing)
481 {
482 struct ub953_data *priv = sd_to_ub953(sd);
483
484 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
485 return -EBUSY;
486
487 return _ub953_set_routing(sd, state, routing);
488 }
489
ub953_get_frame_desc(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_frame_desc * fd)490 static int ub953_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
491 struct v4l2_mbus_frame_desc *fd)
492 {
493 struct ub953_data *priv = sd_to_ub953(sd);
494 struct v4l2_mbus_frame_desc source_fd;
495 struct v4l2_subdev_route *route;
496 struct v4l2_subdev_state *state;
497 int ret;
498
499 if (pad != UB953_PAD_SOURCE)
500 return -EINVAL;
501
502 ret = v4l2_subdev_call(priv->source_sd, pad, get_frame_desc,
503 priv->source_sd_pad, &source_fd);
504 if (ret)
505 return ret;
506
507 memset(fd, 0, sizeof(*fd));
508
509 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
510
511 state = v4l2_subdev_lock_and_get_active_state(sd);
512
513 for_each_active_route(&state->routing, route) {
514 struct v4l2_mbus_frame_desc_entry *source_entry = NULL;
515 unsigned int i;
516
517 if (route->source_pad != pad)
518 continue;
519
520 for (i = 0; i < source_fd.num_entries; i++) {
521 if (source_fd.entry[i].stream == route->sink_stream) {
522 source_entry = &source_fd.entry[i];
523 break;
524 }
525 }
526
527 if (!source_entry) {
528 dev_err(&priv->client->dev,
529 "Failed to find stream from source frame desc\n");
530 ret = -EPIPE;
531 goto out_unlock;
532 }
533
534 fd->entry[fd->num_entries].stream = route->source_stream;
535 fd->entry[fd->num_entries].flags = source_entry->flags;
536 fd->entry[fd->num_entries].length = source_entry->length;
537 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode;
538 fd->entry[fd->num_entries].bus.csi2.vc =
539 source_entry->bus.csi2.vc;
540 fd->entry[fd->num_entries].bus.csi2.dt =
541 source_entry->bus.csi2.dt;
542
543 fd->num_entries++;
544 }
545
546 out_unlock:
547 v4l2_subdev_unlock_state(state);
548
549 return ret;
550 }
551
ub953_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * format)552 static int ub953_set_fmt(struct v4l2_subdev *sd,
553 struct v4l2_subdev_state *state,
554 struct v4l2_subdev_format *format)
555 {
556 struct ub953_data *priv = sd_to_ub953(sd);
557 struct v4l2_mbus_framefmt *fmt;
558
559 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
560 priv->enabled_source_streams)
561 return -EBUSY;
562
563 /* No transcoding, source and sink formats must match. */
564 if (format->pad == UB953_PAD_SOURCE)
565 return v4l2_subdev_get_fmt(sd, state, format);
566
567 /* Set sink format */
568 fmt = v4l2_subdev_state_get_stream_format(state, format->pad,
569 format->stream);
570 if (!fmt)
571 return -EINVAL;
572
573 *fmt = format->format;
574
575 /* Propagate to source format */
576 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
577 format->stream);
578 if (!fmt)
579 return -EINVAL;
580
581 *fmt = format->format;
582
583 return 0;
584 }
585
ub953_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)586 static int ub953_init_cfg(struct v4l2_subdev *sd,
587 struct v4l2_subdev_state *state)
588 {
589 struct v4l2_subdev_route routes[] = {
590 {
591 .sink_pad = UB953_PAD_SINK,
592 .sink_stream = 0,
593 .source_pad = UB953_PAD_SOURCE,
594 .source_stream = 0,
595 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
596 },
597 };
598
599 struct v4l2_subdev_krouting routing = {
600 .num_routes = ARRAY_SIZE(routes),
601 .routes = routes,
602 };
603
604 return _ub953_set_routing(sd, state, &routing);
605 }
606
ub953_log_status(struct v4l2_subdev * sd)607 static int ub953_log_status(struct v4l2_subdev *sd)
608 {
609 struct ub953_data *priv = sd_to_ub953(sd);
610 struct device *dev = &priv->client->dev;
611 u8 v = 0, v1 = 0, v2 = 0;
612 unsigned int i;
613 char id[UB953_REG_FPD3_RX_ID_LEN];
614 u8 gpio_local_data = 0;
615 u8 gpio_input_ctrl = 0;
616 u8 gpio_pin_sts = 0;
617
618 for (i = 0; i < sizeof(id); i++)
619 ub953_read(priv, UB953_REG_FPD3_RX_ID(i), &id[i]);
620
621 dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
622
623 ub953_read(priv, UB953_REG_GENERAL_STATUS, &v);
624 dev_info(dev, "GENERAL_STATUS %#02x\n", v);
625
626 ub953_read(priv, UB953_REG_CRC_ERR_CNT1, &v1);
627 ub953_read(priv, UB953_REG_CRC_ERR_CNT2, &v2);
628 dev_info(dev, "CRC error count %u\n", v1 | (v2 << 8));
629
630 ub953_read(priv, UB953_REG_CSI_ERR_CNT, &v);
631 dev_info(dev, "CSI error count %u\n", v);
632
633 ub953_read(priv, UB953_REG_CSI_ERR_STATUS, &v);
634 dev_info(dev, "CSI_ERR_STATUS %#02x\n", v);
635
636 ub953_read(priv, UB953_REG_CSI_ERR_DLANE01, &v);
637 dev_info(dev, "CSI_ERR_DLANE01 %#02x\n", v);
638
639 ub953_read(priv, UB953_REG_CSI_ERR_DLANE23, &v);
640 dev_info(dev, "CSI_ERR_DLANE23 %#02x\n", v);
641
642 ub953_read(priv, UB953_REG_CSI_ERR_CLK_LANE, &v);
643 dev_info(dev, "CSI_ERR_CLK_LANE %#02x\n", v);
644
645 ub953_read(priv, UB953_REG_CSI_PKT_HDR_VC_ID, &v);
646 dev_info(dev, "CSI packet header VC %u ID %u\n", v >> 6, v & 0x3f);
647
648 ub953_read(priv, UB953_REG_PKT_HDR_WC_LSB, &v1);
649 ub953_read(priv, UB953_REG_PKT_HDR_WC_MSB, &v2);
650 dev_info(dev, "CSI packet header WC %u\n", (v2 << 8) | v1);
651
652 ub953_read(priv, UB953_REG_CSI_ECC, &v);
653 dev_info(dev, "CSI ECC %#02x\n", v);
654
655 ub953_read(priv, UB953_REG_LOCAL_GPIO_DATA, &gpio_local_data);
656 ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &gpio_input_ctrl);
657 ub953_read(priv, UB953_REG_GPIO_PIN_STS, &gpio_pin_sts);
658
659 for (i = 0; i < UB953_NUM_GPIOS; i++) {
660 dev_info(dev,
661 "GPIO%u: remote: %u is_input: %u is_output: %u val: %u sts: %u\n",
662 i,
663 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(i)),
664 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(i)),
665 !!(gpio_input_ctrl & UB953_REG_GPIO_INPUT_CTRL_OUT_EN(i)),
666 !!(gpio_local_data & UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(i)),
667 !!(gpio_pin_sts & UB953_REG_GPIO_PIN_STS_GPIO_STS(i)));
668 }
669
670 return 0;
671 }
672
ub953_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)673 static int ub953_enable_streams(struct v4l2_subdev *sd,
674 struct v4l2_subdev_state *state, u32 pad,
675 u64 streams_mask)
676 {
677 struct ub953_data *priv = sd_to_ub953(sd);
678 u64 sink_streams;
679 int ret;
680
681 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE,
682 UB953_PAD_SINK,
683 &streams_mask);
684
685 ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad,
686 sink_streams);
687 if (ret)
688 return ret;
689
690 priv->enabled_source_streams |= streams_mask;
691
692 return 0;
693 }
694
ub953_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)695 static int ub953_disable_streams(struct v4l2_subdev *sd,
696 struct v4l2_subdev_state *state, u32 pad,
697 u64 streams_mask)
698 {
699 struct ub953_data *priv = sd_to_ub953(sd);
700 u64 sink_streams;
701 int ret;
702
703 sink_streams = v4l2_subdev_state_xlate_streams(state, UB953_PAD_SOURCE,
704 UB953_PAD_SINK,
705 &streams_mask);
706
707 ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad,
708 sink_streams);
709 if (ret)
710 return ret;
711
712 priv->enabled_source_streams &= ~streams_mask;
713
714 return 0;
715 }
716
717 static const struct v4l2_subdev_pad_ops ub953_pad_ops = {
718 .enable_streams = ub953_enable_streams,
719 .disable_streams = ub953_disable_streams,
720 .set_routing = ub953_set_routing,
721 .get_frame_desc = ub953_get_frame_desc,
722 .get_fmt = v4l2_subdev_get_fmt,
723 .set_fmt = ub953_set_fmt,
724 .init_cfg = ub953_init_cfg,
725 };
726
727 static const struct v4l2_subdev_core_ops ub953_subdev_core_ops = {
728 .log_status = ub953_log_status,
729 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
730 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
731 };
732
733 static const struct v4l2_subdev_ops ub953_subdev_ops = {
734 .core = &ub953_subdev_core_ops,
735 .pad = &ub953_pad_ops,
736 };
737
738 static const struct media_entity_operations ub953_entity_ops = {
739 .link_validate = v4l2_subdev_link_validate,
740 };
741
ub953_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * source_subdev,struct v4l2_async_connection * asd)742 static int ub953_notify_bound(struct v4l2_async_notifier *notifier,
743 struct v4l2_subdev *source_subdev,
744 struct v4l2_async_connection *asd)
745 {
746 struct ub953_data *priv = sd_to_ub953(notifier->sd);
747 struct device *dev = &priv->client->dev;
748 int ret;
749
750 ret = media_entity_get_fwnode_pad(&source_subdev->entity,
751 source_subdev->fwnode,
752 MEDIA_PAD_FL_SOURCE);
753 if (ret < 0) {
754 dev_err(dev, "Failed to find pad for %s\n",
755 source_subdev->name);
756 return ret;
757 }
758
759 priv->source_sd = source_subdev;
760 priv->source_sd_pad = ret;
761
762 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,
763 &priv->sd.entity, 0,
764 MEDIA_LNK_FL_ENABLED |
765 MEDIA_LNK_FL_IMMUTABLE);
766 if (ret) {
767 dev_err(dev, "Unable to link %s:%u -> %s:0\n",
768 source_subdev->name, priv->source_sd_pad,
769 priv->sd.name);
770 return ret;
771 }
772
773 return 0;
774 }
775
776 static const struct v4l2_async_notifier_operations ub953_notify_ops = {
777 .bound = ub953_notify_bound,
778 };
779
ub953_v4l2_notifier_register(struct ub953_data * priv)780 static int ub953_v4l2_notifier_register(struct ub953_data *priv)
781 {
782 struct device *dev = &priv->client->dev;
783 struct v4l2_async_connection *asd;
784 struct fwnode_handle *ep_fwnode;
785 int ret;
786
787 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
788 UB953_PAD_SINK, 0, 0);
789 if (!ep_fwnode) {
790 dev_err(dev, "No graph endpoint\n");
791 return -ENODEV;
792 }
793
794 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
795
796 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,
797 struct v4l2_async_connection);
798
799 fwnode_handle_put(ep_fwnode);
800
801 if (IS_ERR(asd)) {
802 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd));
803 v4l2_async_nf_cleanup(&priv->notifier);
804 return PTR_ERR(asd);
805 }
806
807 priv->notifier.ops = &ub953_notify_ops;
808
809 ret = v4l2_async_nf_register(&priv->notifier);
810 if (ret) {
811 dev_err(dev, "Failed to register subdev_notifier");
812 v4l2_async_nf_cleanup(&priv->notifier);
813 return ret;
814 }
815
816 return 0;
817 }
818
ub953_v4l2_notifier_unregister(struct ub953_data * priv)819 static void ub953_v4l2_notifier_unregister(struct ub953_data *priv)
820 {
821 v4l2_async_nf_unregister(&priv->notifier);
822 v4l2_async_nf_cleanup(&priv->notifier);
823 }
824
825 /*
826 * Probing
827 */
828
ub953_i2c_master_init(struct ub953_data * priv)829 static int ub953_i2c_master_init(struct ub953_data *priv)
830 {
831 /* i2c fast mode */
832 u32 ref = 26250000;
833 u32 scl_high = 915; /* ns */
834 u32 scl_low = 1641; /* ns */
835 int ret;
836
837 scl_high = div64_u64((u64)scl_high * ref, 1000000000) - 5;
838 scl_low = div64_u64((u64)scl_low * ref, 1000000000) - 5;
839
840 ret = ub953_write(priv, UB953_REG_SCL_HIGH_TIME, scl_high);
841 if (ret)
842 return ret;
843
844 ret = ub953_write(priv, UB953_REG_SCL_LOW_TIME, scl_low);
845 if (ret)
846 return ret;
847
848 return 0;
849 }
850
ub953_get_fc_rate(struct ub953_data * priv)851 static u64 ub953_get_fc_rate(struct ub953_data *priv)
852 {
853 switch (priv->mode) {
854 case UB953_MODE_SYNC:
855 if (priv->hw_data->is_ub971)
856 return priv->plat_data->bc_rate * 160ull;
857 else
858 return priv->plat_data->bc_rate / 2 * 160ull;
859
860 case UB953_MODE_NONSYNC_EXT:
861 /* CLKIN_DIV = 1 always */
862 return clk_get_rate(priv->clkin) * 80ull;
863
864 default:
865 /* Not supported */
866 return 0;
867 }
868 }
869
ub953_calc_clkout_ub953(struct ub953_data * priv,unsigned long target,u64 fc,u8 * hs_div,u8 * m,u8 * n)870 static unsigned long ub953_calc_clkout_ub953(struct ub953_data *priv,
871 unsigned long target, u64 fc,
872 u8 *hs_div, u8 *m, u8 *n)
873 {
874 /*
875 * We always use 4 as a pre-divider (HS_CLK_DIV = 2).
876 *
877 * According to the datasheet:
878 * - "HS_CLK_DIV typically should be set to either 16, 8, or 4 (default)."
879 * - "if it is not possible to have an integer ratio of N/M, it is best to
880 * select a smaller value for HS_CLK_DIV.
881 *
882 * For above reasons the default HS_CLK_DIV seems the best in the average
883 * case. Use always that value to keep the code simple.
884 */
885 static const unsigned long hs_clk_div = 4;
886
887 u64 fc_divided;
888 unsigned long mul, div;
889 unsigned long res;
890
891 /* clkout = fc / hs_clk_div * m / n */
892
893 fc_divided = div_u64(fc, hs_clk_div);
894
895 rational_best_approximation(target, fc_divided, (1 << 5) - 1,
896 (1 << 8) - 1, &mul, &div);
897
898 res = div_u64(fc_divided * mul, div);
899
900 *hs_div = hs_clk_div;
901 *m = mul;
902 *n = div;
903
904 return res;
905 }
906
ub953_calc_clkout_ub971(struct ub953_data * priv,unsigned long target,u64 fc,u8 * m,u8 * n)907 static unsigned long ub953_calc_clkout_ub971(struct ub953_data *priv,
908 unsigned long target, u64 fc,
909 u8 *m, u8 *n)
910 {
911 u64 fc_divided;
912 unsigned long mul, div;
913 unsigned long res;
914
915 /* clkout = fc * m / (8 * n) */
916
917 fc_divided = div_u64(fc, 8);
918
919 rational_best_approximation(target, fc_divided, (1 << 5) - 1,
920 (1 << 8) - 1, &mul, &div);
921
922 res = div_u64(fc_divided * mul, div);
923
924 *m = mul;
925 *n = div;
926
927 return res;
928 }
929
ub953_calc_clkout_params(struct ub953_data * priv,unsigned long target_rate,struct ub953_clkout_data * clkout_data)930 static void ub953_calc_clkout_params(struct ub953_data *priv,
931 unsigned long target_rate,
932 struct ub953_clkout_data *clkout_data)
933 {
934 struct device *dev = &priv->client->dev;
935 unsigned long clkout_rate;
936 u64 fc_rate;
937
938 fc_rate = ub953_get_fc_rate(priv);
939
940 if (priv->hw_data->is_ub971) {
941 u8 m, n;
942
943 clkout_rate = ub953_calc_clkout_ub971(priv, target_rate,
944 fc_rate, &m, &n);
945
946 clkout_data->m = m;
947 clkout_data->n = n;
948
949 dev_dbg(dev, "%s %llu * %u / (8 * %u) = %lu (requested %lu)",
950 __func__, fc_rate, m, n, clkout_rate, target_rate);
951 } else {
952 u8 hs_div, m, n;
953
954 clkout_rate = ub953_calc_clkout_ub953(priv, target_rate,
955 fc_rate, &hs_div, &m, &n);
956
957 clkout_data->hs_div = hs_div;
958 clkout_data->m = m;
959 clkout_data->n = n;
960
961 dev_dbg(dev, "%s %llu / %u * %u / %u = %lu (requested %lu)",
962 __func__, fc_rate, hs_div, m, n, clkout_rate,
963 target_rate);
964 }
965
966 clkout_data->rate = clkout_rate;
967 }
968
ub953_write_clkout_regs(struct ub953_data * priv,const struct ub953_clkout_data * clkout_data)969 static int ub953_write_clkout_regs(struct ub953_data *priv,
970 const struct ub953_clkout_data *clkout_data)
971 {
972 u8 clkout_ctrl0, clkout_ctrl1;
973 int ret;
974
975 if (priv->hw_data->is_ub971)
976 clkout_ctrl0 = clkout_data->m;
977 else
978 clkout_ctrl0 = (__ffs(clkout_data->hs_div) << 5) |
979 clkout_data->m;
980
981 clkout_ctrl1 = clkout_data->n;
982
983 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL0, clkout_ctrl0);
984 if (ret)
985 return ret;
986
987 ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL1, clkout_ctrl1);
988 if (ret)
989 return ret;
990
991 return 0;
992 }
993
ub953_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)994 static unsigned long ub953_clkout_recalc_rate(struct clk_hw *hw,
995 unsigned long parent_rate)
996 {
997 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
998 struct device *dev = &priv->client->dev;
999 u8 ctrl0, ctrl1;
1000 u32 mul, div;
1001 u64 fc_rate;
1002 u32 hs_clk_div;
1003 u64 rate;
1004 int ret;
1005
1006 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL0, &ctrl0);
1007 if (ret) {
1008 dev_err(dev, "Failed to read CLKOUT_CTRL0: %d\n", ret);
1009 return 0;
1010 }
1011
1012 ret = ub953_read(priv, UB953_REG_CLKOUT_CTRL1, &ctrl1);
1013 if (ret) {
1014 dev_err(dev, "Failed to read CLKOUT_CTRL1: %d\n", ret);
1015 return 0;
1016 }
1017
1018 fc_rate = ub953_get_fc_rate(priv);
1019
1020 if (priv->hw_data->is_ub971) {
1021 mul = ctrl0 & 0x1f;
1022 div = ctrl1;
1023
1024 if (div == 0)
1025 return 0;
1026
1027 rate = div_u64(fc_rate * mul, 8 * div);
1028
1029 dev_dbg(dev, "clkout: fc rate %llu, mul %u, div %u = %llu\n",
1030 fc_rate, mul, div, rate);
1031 } else {
1032 mul = ctrl0 & 0x1f;
1033 hs_clk_div = 1 << (ctrl0 >> 5);
1034 div = ctrl1;
1035
1036 if (div == 0)
1037 return 0;
1038
1039 rate = div_u64(div_u64(fc_rate, hs_clk_div) * mul, div);
1040
1041 dev_dbg(dev,
1042 "clkout: fc rate %llu, hs_clk_div %u, mul %u, div %u = %llu\n",
1043 fc_rate, hs_clk_div, mul, div, rate);
1044 }
1045
1046 return rate;
1047 }
1048
ub953_clkout_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1049 static long ub953_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
1050 unsigned long *parent_rate)
1051 {
1052 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
1053 struct ub953_clkout_data clkout_data;
1054
1055 ub953_calc_clkout_params(priv, rate, &clkout_data);
1056
1057 return clkout_data.rate;
1058 }
1059
ub953_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1060 static int ub953_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1061 unsigned long parent_rate)
1062 {
1063 struct ub953_data *priv = container_of(hw, struct ub953_data, clkout_clk_hw);
1064 struct ub953_clkout_data clkout_data;
1065
1066 ub953_calc_clkout_params(priv, rate, &clkout_data);
1067
1068 dev_dbg(&priv->client->dev, "%s %lu (requested %lu)\n", __func__,
1069 clkout_data.rate, rate);
1070
1071 return ub953_write_clkout_regs(priv, &clkout_data);
1072 }
1073
1074 static const struct clk_ops ub953_clkout_ops = {
1075 .recalc_rate = ub953_clkout_recalc_rate,
1076 .round_rate = ub953_clkout_round_rate,
1077 .set_rate = ub953_clkout_set_rate,
1078 };
1079
ub953_register_clkout(struct ub953_data * priv)1080 static int ub953_register_clkout(struct ub953_data *priv)
1081 {
1082 struct device *dev = &priv->client->dev;
1083 const struct clk_init_data init = {
1084 .name = kasprintf(GFP_KERNEL, "ds90%s.%s.clk_out",
1085 priv->hw_data->model, dev_name(dev)),
1086 .ops = &ub953_clkout_ops,
1087 };
1088 struct ub953_clkout_data clkout_data;
1089 int ret;
1090
1091 if (!init.name)
1092 return -ENOMEM;
1093
1094 /* Initialize clkout to 25MHz by default */
1095 ub953_calc_clkout_params(priv, UB953_DEFAULT_CLKOUT_RATE, &clkout_data);
1096 ret = ub953_write_clkout_regs(priv, &clkout_data);
1097 if (ret)
1098 return ret;
1099
1100 priv->clkout_clk_hw.init = &init;
1101
1102 ret = devm_clk_hw_register(dev, &priv->clkout_clk_hw);
1103 kfree(init.name);
1104 if (ret)
1105 return dev_err_probe(dev, ret, "Cannot register clock HW\n");
1106
1107 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1108 &priv->clkout_clk_hw);
1109 if (ret)
1110 return dev_err_probe(dev, ret,
1111 "Cannot add OF clock provider\n");
1112
1113 return 0;
1114 }
1115
ub953_add_i2c_adapter(struct ub953_data * priv)1116 static int ub953_add_i2c_adapter(struct ub953_data *priv)
1117 {
1118 struct device *dev = &priv->client->dev;
1119 struct fwnode_handle *i2c_handle;
1120 int ret;
1121
1122 i2c_handle = device_get_named_child_node(dev, "i2c");
1123 if (!i2c_handle)
1124 return 0;
1125
1126 ret = i2c_atr_add_adapter(priv->plat_data->atr, priv->plat_data->port,
1127 dev, i2c_handle);
1128
1129 fwnode_handle_put(i2c_handle);
1130
1131 if (ret)
1132 return ret;
1133
1134 return 0;
1135 }
1136
1137 static const struct regmap_config ub953_regmap_config = {
1138 .name = "ds90ub953",
1139 .reg_bits = 8,
1140 .val_bits = 8,
1141 .reg_format_endian = REGMAP_ENDIAN_DEFAULT,
1142 .val_format_endian = REGMAP_ENDIAN_DEFAULT,
1143 };
1144
ub953_parse_dt(struct ub953_data * priv)1145 static int ub953_parse_dt(struct ub953_data *priv)
1146 {
1147 struct device *dev = &priv->client->dev;
1148 struct v4l2_fwnode_endpoint vep = {
1149 .bus_type = V4L2_MBUS_CSI2_DPHY,
1150 };
1151 struct fwnode_handle *ep_fwnode;
1152 unsigned char nlanes;
1153 int ret;
1154
1155 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
1156 UB953_PAD_SINK, 0, 0);
1157 if (!ep_fwnode)
1158 return dev_err_probe(dev, -ENOENT, "no endpoint found\n");
1159
1160 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
1161
1162 fwnode_handle_put(ep_fwnode);
1163
1164 if (ret)
1165 return dev_err_probe(dev, ret,
1166 "failed to parse sink endpoint data\n");
1167
1168 nlanes = vep.bus.mipi_csi2.num_data_lanes;
1169 if (nlanes != 1 && nlanes != 2 && nlanes != 4)
1170 return dev_err_probe(dev, -EINVAL,
1171 "bad number of data-lanes: %u\n", nlanes);
1172
1173 priv->num_data_lanes = nlanes;
1174
1175 priv->non_continous_clk = vep.bus.mipi_csi2.flags &
1176 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
1177
1178 return 0;
1179 }
1180
ub953_hw_init(struct ub953_data * priv)1181 static int ub953_hw_init(struct ub953_data *priv)
1182 {
1183 struct device *dev = &priv->client->dev;
1184 bool mode_override;
1185 int ret;
1186 u8 v;
1187
1188 ret = ub953_read(priv, UB953_REG_MODE_SEL, &v);
1189 if (ret)
1190 return ret;
1191
1192 if (!(v & UB953_REG_MODE_SEL_MODE_DONE))
1193 return dev_err_probe(dev, -EIO, "Mode value not stabilized\n");
1194
1195 mode_override = v & UB953_REG_MODE_SEL_MODE_OVERRIDE;
1196
1197 switch (v & UB953_REG_MODE_SEL_MODE_MASK) {
1198 case 0:
1199 priv->mode = UB953_MODE_SYNC;
1200 break;
1201 case 2:
1202 priv->mode = UB953_MODE_NONSYNC_EXT;
1203 break;
1204 case 3:
1205 priv->mode = UB953_MODE_NONSYNC_INT;
1206 break;
1207 case 5:
1208 priv->mode = UB953_MODE_DVP;
1209 break;
1210 default:
1211 return dev_err_probe(dev, -EIO,
1212 "Invalid mode in mode register\n");
1213 }
1214
1215 dev_dbg(dev, "mode from %s: %#x\n", mode_override ? "reg" : "strap",
1216 priv->mode);
1217
1218 if (priv->mode != UB953_MODE_SYNC &&
1219 priv->mode != UB953_MODE_NONSYNC_EXT)
1220 return dev_err_probe(dev, -ENODEV,
1221 "Unsupported mode selected: %u\n",
1222 priv->mode);
1223
1224 if (priv->mode == UB953_MODE_NONSYNC_EXT && !priv->clkin)
1225 return dev_err_probe(dev, -EINVAL,
1226 "clkin required for non-sync ext mode\n");
1227
1228 ret = ub953_read(priv, UB953_REG_REV_MASK_ID, &v);
1229 if (ret)
1230 return dev_err_probe(dev, ret, "Failed to read revision");
1231
1232 dev_info(dev, "Found %s rev/mask %#04x\n", priv->hw_data->model, v);
1233
1234 ret = ub953_read(priv, UB953_REG_GENERAL_CFG, &v);
1235 if (ret)
1236 return ret;
1237
1238 dev_dbg(dev, "i2c strap setting %s V\n",
1239 (v & UB953_REG_GENERAL_CFG_I2C_STRAP_MODE) ? "1.8" : "3.3");
1240
1241 ret = ub953_i2c_master_init(priv);
1242 if (ret)
1243 return dev_err_probe(dev, ret, "i2c init failed\n");
1244
1245 v = 0;
1246 v |= priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK;
1247 v |= (priv->num_data_lanes - 1) <<
1248 UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT;
1249 v |= UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE;
1250
1251 ret = ub953_write(priv, UB953_REG_GENERAL_CFG, v);
1252 if (ret)
1253 return ret;
1254
1255 return 0;
1256 }
1257
ub953_subdev_init(struct ub953_data * priv)1258 static int ub953_subdev_init(struct ub953_data *priv)
1259 {
1260 struct device *dev = &priv->client->dev;
1261 int ret;
1262
1263 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub953_subdev_ops);
1264
1265 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1266 V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS;
1267 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1268 priv->sd.entity.ops = &ub953_entity_ops;
1269
1270 priv->pads[0].flags = MEDIA_PAD_FL_SINK;
1271 priv->pads[1].flags = MEDIA_PAD_FL_SOURCE;
1272
1273 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);
1274 if (ret)
1275 return dev_err_probe(dev, ret, "Failed to init pads\n");
1276
1277 ret = v4l2_subdev_init_finalize(&priv->sd);
1278 if (ret)
1279 goto err_entity_cleanup;
1280
1281 ret = ub953_v4l2_notifier_register(priv);
1282 if (ret) {
1283 dev_err_probe(dev, ret,
1284 "v4l2 subdev notifier register failed\n");
1285 goto err_free_state;
1286 }
1287
1288 ret = v4l2_async_register_subdev(&priv->sd);
1289 if (ret) {
1290 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n");
1291 goto err_unreg_notif;
1292 }
1293
1294 return 0;
1295
1296 err_unreg_notif:
1297 ub953_v4l2_notifier_unregister(priv);
1298 err_free_state:
1299 v4l2_subdev_cleanup(&priv->sd);
1300 err_entity_cleanup:
1301 media_entity_cleanup(&priv->sd.entity);
1302
1303 return ret;
1304 }
1305
ub953_subdev_uninit(struct ub953_data * priv)1306 static void ub953_subdev_uninit(struct ub953_data *priv)
1307 {
1308 v4l2_async_unregister_subdev(&priv->sd);
1309 ub953_v4l2_notifier_unregister(priv);
1310 v4l2_subdev_cleanup(&priv->sd);
1311 media_entity_cleanup(&priv->sd.entity);
1312 }
1313
ub953_probe(struct i2c_client * client)1314 static int ub953_probe(struct i2c_client *client)
1315 {
1316 struct device *dev = &client->dev;
1317 struct ub953_data *priv;
1318 int ret;
1319
1320 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1321 if (!priv)
1322 return -ENOMEM;
1323
1324 priv->client = client;
1325
1326 priv->hw_data = device_get_match_data(dev);
1327
1328 priv->plat_data = dev_get_platdata(&client->dev);
1329 if (!priv->plat_data)
1330 return dev_err_probe(dev, -ENODEV, "Platform data missing\n");
1331
1332 mutex_init(&priv->reg_lock);
1333
1334 /*
1335 * Initialize to invalid values so that the first reg writes will
1336 * configure the target.
1337 */
1338 priv->current_indirect_target = 0xff;
1339
1340 priv->regmap = devm_regmap_init_i2c(client, &ub953_regmap_config);
1341 if (IS_ERR(priv->regmap)) {
1342 ret = PTR_ERR(priv->regmap);
1343 dev_err_probe(dev, ret, "Failed to init regmap\n");
1344 goto err_mutex_destroy;
1345 }
1346
1347 priv->clkin = devm_clk_get_optional(dev, "clkin");
1348 if (IS_ERR(priv->clkin)) {
1349 ret = PTR_ERR(priv->clkin);
1350 dev_err_probe(dev, ret, "failed to parse 'clkin'\n");
1351 goto err_mutex_destroy;
1352 }
1353
1354 ret = ub953_parse_dt(priv);
1355 if (ret)
1356 goto err_mutex_destroy;
1357
1358 ret = ub953_hw_init(priv);
1359 if (ret)
1360 goto err_mutex_destroy;
1361
1362 ret = ub953_gpiochip_probe(priv);
1363 if (ret) {
1364 dev_err_probe(dev, ret, "Failed to init gpiochip\n");
1365 goto err_mutex_destroy;
1366 }
1367
1368 ret = ub953_register_clkout(priv);
1369 if (ret) {
1370 dev_err_probe(dev, ret, "Failed to register clkout\n");
1371 goto err_gpiochip_remove;
1372 }
1373
1374 ret = ub953_subdev_init(priv);
1375 if (ret)
1376 goto err_gpiochip_remove;
1377
1378 ret = ub953_add_i2c_adapter(priv);
1379 if (ret) {
1380 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n");
1381 goto err_subdev_uninit;
1382 }
1383
1384 return 0;
1385
1386 err_subdev_uninit:
1387 ub953_subdev_uninit(priv);
1388 err_gpiochip_remove:
1389 ub953_gpiochip_remove(priv);
1390 err_mutex_destroy:
1391 mutex_destroy(&priv->reg_lock);
1392
1393 return ret;
1394 }
1395
ub953_remove(struct i2c_client * client)1396 static void ub953_remove(struct i2c_client *client)
1397 {
1398 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1399 struct ub953_data *priv = sd_to_ub953(sd);
1400
1401 i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port);
1402
1403 ub953_subdev_uninit(priv);
1404
1405 ub953_gpiochip_remove(priv);
1406 mutex_destroy(&priv->reg_lock);
1407 }
1408
1409 static const struct ub953_hw_data ds90ub953_hw = {
1410 .model = "ub953",
1411 };
1412
1413 static const struct ub953_hw_data ds90ub971_hw = {
1414 .model = "ub971",
1415 .is_ub971 = true,
1416 };
1417
1418 static const struct i2c_device_id ub953_id[] = {
1419 { "ds90ub953-q1", (kernel_ulong_t)&ds90ub953_hw },
1420 { "ds90ub971-q1", (kernel_ulong_t)&ds90ub971_hw },
1421 {}
1422 };
1423 MODULE_DEVICE_TABLE(i2c, ub953_id);
1424
1425 static const struct of_device_id ub953_dt_ids[] = {
1426 { .compatible = "ti,ds90ub953-q1", .data = &ds90ub953_hw },
1427 { .compatible = "ti,ds90ub971-q1", .data = &ds90ub971_hw },
1428 {}
1429 };
1430 MODULE_DEVICE_TABLE(of, ub953_dt_ids);
1431
1432 static struct i2c_driver ds90ub953_driver = {
1433 .probe = ub953_probe,
1434 .remove = ub953_remove,
1435 .id_table = ub953_id,
1436 .driver = {
1437 .name = "ds90ub953",
1438 .of_match_table = ub953_dt_ids,
1439 },
1440 };
1441 module_i2c_driver(ds90ub953_driver);
1442
1443 MODULE_LICENSE("GPL");
1444 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV CSI-2 Serializers Driver");
1445 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
1446 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
1447 MODULE_IMPORT_NS(I2C_ATR);
1448