1// SPDX-License-Identifier: GPL-2.0+ 2/dts-v1/; 3 4#include "aspeed-g6.dtsi" 5#include <dt-bindings/i2c/i2c.h> 6#include <dt-bindings/gpio/aspeed-gpio.h> 7#include <dt-bindings/leds/common.h> 8 9/ { 10 model = "AST2600 GB200NVL BMC"; 11 compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600"; 12 13 aliases { 14 serial2 = &uart3; 15 serial4 = &uart5; 16 i2c16 = &imux16; 17 i2c17 = &imux17; 18 i2c18 = &imux18; 19 i2c19 = &imux19; 20 i2c20 = &imux20; 21 i2c21 = &imux21; 22 i2c22 = &imux22; 23 i2c23 = &imux23; 24 i2c24 = &imux24; 25 i2c25 = &imux25; 26 i2c26 = &imux26; 27 i2c27 = &imux27; 28 i2c28 = &imux28; 29 i2c29 = &imux29; 30 i2c30 = &imux30; 31 i2c31 = &imux31; 32 i2c32 = &imux32; 33 i2c33 = &imux33; 34 i2c34 = &imux34; 35 i2c35 = &imux35; 36 i2c36 = &imux36; 37 i2c37 = &imux37; 38 i2c38 = &imux38; 39 i2c39 = &imux39; 40 i2c40 = &e1si2c0; 41 i2c41 = &e1si2c1; 42 i2c42 = &e1si2c2; 43 i2c43 = &e1si2c3; 44 i2c44 = &e1si2c4; 45 i2c45 = &e1si2c5; 46 i2c46 = &e1si2c6; 47 i2c47 = &e1si2c7; 48 i2c48 = &i2c17mux0; 49 i2c49 = &i2c17mux1; 50 i2c50 = &i2c17mux2; 51 i2c51 = &i2c17mux3; 52 i2c52 = &i2c25mux0; 53 i2c53 = &i2c25mux1; 54 i2c54 = &i2c25mux2; 55 i2c55 = &i2c25mux3; 56 i2c56 = &i2c29mux0; 57 i2c57 = &i2c29mux1; 58 i2c58 = &i2c29mux2; 59 i2c59 = &i2c29mux3; 60 }; 61 62 chosen { 63 stdout-path = &uart5; 64 }; 65 66 memory@80000000 { 67 device_type = "memory"; 68 reg = <0x80000000 0x80000000>; 69 }; 70 71 reserved-memory { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges; 75 76 vga_memory: framebuffer@9f000000 { 77 no-map; 78 reg = <0x9f000000 0x01000000>; /* 16M */ 79 }; 80 81 ramoops@a0000000 { 82 compatible = "ramoops"; 83 reg = <0xa0000000 0x100000>; /* 1MB */ 84 record-size = <0x10000>; /* 64KB */ 85 max-reason = <2>; /* KMSG_DUMP_OOPS */ 86 }; 87 88 gfx_memory: framebuffer { 89 size = <0x01000000>; 90 alignment = <0x01000000>; 91 compatible = "shared-dma-pool"; 92 reusable; 93 }; 94 95 video_engine_memory: jpegbuffer { 96 size = <0x02000000>; /* 32M */ 97 alignment = <0x01000000>; 98 compatible = "shared-dma-pool"; 99 reusable; 100 }; 101 }; 102 103 leds { 104 compatible = "gpio-leds"; 105 led-0 { 106 label = "uid_led"; 107 gpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>; 108 }; 109 led-1 { 110 label = "fault_led"; 111 gpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>; 112 }; 113 led-2 { 114 label = "power_led"; 115 gpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>; 116 }; 117 }; 118 119 buttons { 120 button-power { 121 label = "power-btn"; 122 gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>; 123 }; 124 button-uid { 125 label = "uid-btn"; 126 gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>; 127 }; 128 }; 129}; 130 131// Enable Primary flash on FMC for bring up activity 132&fmc { 133 status = "okay"; 134 flash@0 { 135 status = "okay"; 136 compatible = "jedec,spi-nor"; 137 label = "bmc"; 138 spi-max-frequency = <50000000>; 139 partitions { 140 compatible = "fixed-partitions"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 144 u-boot@0 { 145 // 896KB 146 reg = <0x0 0xe0000>; 147 label = "u-boot"; 148 }; 149 150 kernel@100000 { 151 // 9MB 152 reg = <0x100000 0x900000>; 153 label = "kernel"; 154 }; 155 156 rofs@a00000 { 157 // 55292KB (extends to end of 64MB SPI - 4KB) 158 reg = <0xa00000 0x35FF000>; 159 label = "rofs"; 160 }; 161 }; 162 }; 163}; 164 165&spi2 { 166 status = "okay"; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_spi2_default>; 169 170 // Data SPI is 64MB in size 171 flash@0 { 172 status = "okay"; 173 label = "config"; 174 spi-max-frequency = <50000000>; 175 partitions { 176 compatible = "fixed-partitions"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 180 u-boot-env@0 { 181 // 256KB 182 reg = <0x0 0x40000>; 183 label = "u-boot-env"; 184 }; 185 186 rwfs@40000 { 187 // 16MB 188 reg = <0x40000 0x1000000>; 189 label = "rwfs"; 190 }; 191 192 log@1040000 { 193 // 40MB 194 reg = <0x1040000 0x2800000>; 195 label = "log"; 196 }; 197 }; 198 }; 199}; 200 201&uart1 { 202 status = "okay"; 203}; 204 205&uart3 { 206 // Enabling SOL 207 status = "okay"; 208}; 209 210&uart5 { 211 // BMC Debug Console 212 status = "okay"; 213}; 214 215&uart_routing { 216 status = "okay"; 217}; 218 219&mac2 { 220 status = "okay"; 221 phy-mode = "rmii"; 222 use-ncsi; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_rmii3_default>; 225}; 226 227/* 228 * Enable USB port A as device (via the virtual hub) to host 229 */ 230&vhub { 231 status = "okay"; 232}; 233 234&video { 235 status = "okay"; 236 memory-region = <&video_engine_memory>; 237}; 238 239// USB 2.0 to HMC, on USB Port B 240&ehci1 { 241 status = "okay"; 242}; 243 244// USB 1.0 245&uhci { 246 status = "okay"; 247}; 248 249&sgpiom0 { 250 status="okay"; 251 ngpios = <128>; 252 gpio-line-names = 253 "","", 254 "","", 255 "","", 256 "","", 257 "","", 258 "","", 259 "","", 260 "","", 261 "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O", 262 "RUN_POWER_PG-I","PWR_BRAKE_L-O", 263 "SYS_RST_OUT_L-I","RUN_POWER_EN-O", 264 "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O", 265 "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O", 266 "SHDN_OK_L-I","UID_LED_N-O", 267 "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O", 268 "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O", 269 "FPGA_RSVD_FFU3-I","", 270 "FPGA_RSVD_FFU2-I","", 271 "FPGA_RSVD_FFU1-I","", 272 "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O", 273 "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O", 274 "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O", 275 "THERM_BB_WARN_L-I","UART_MUX_SEL-O", 276 "THERM_BB_OVERT_L-I","", 277 "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O", 278 "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O", 279 "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O", 280 "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O", 281 "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O", 282 "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O", 283 "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O", 284 "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O", 285 "CPU1_UPHY3_PRSNT1_L-I","", 286 "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS", 287 "CPU1_UPHY2_PRSNT1_L-I","", 288 "CPU1_UPHY2_PRSNT0_L-I","", 289 "CPU1_UPHY1_PRSNT1_L-I","", 290 "CPU1_UPHY1_PRSNT0_L-I","", 291 "CPU1_UPHY0_PRSNT1_L-I","", 292 "CPU1_UPHY0_PRSNT0_L-I","", 293 "FAN1_PRESENT_L-I","", 294 "FAN0_PRESENT_L-I","", 295 "","", 296 "IPEX_CABLE_PRSNT_L-I","", 297 "M2_1_PRSNT_L-I","", 298 "M2_0_PRSNT_L-I","", 299 "CPU1_UPHY4_PRSNT1_L-I","", 300 "CPU0_UPHY4_PRSNT0_L-I","", 301 "","", 302 "I2C_RTC_ALERT_L-I","", 303 "FAN7_PRESENT_L-I","", 304 "FAN6_PRESENT_L-I","", 305 "FAN5_PRESENT_L-I","", 306 "FAN4_PRESENT_L-I","", 307 "FAN3_PRESENT_L-I","", 308 "FAN2_PRESENT_L-I","", 309 "IOBRD0_IOX_INT_L-I","", 310 "IOBRD1_PRSNT_L-I","", 311 "IOBRD0_PRSNT_L-I","", 312 "IOBRD1_PWR_GOOD-I","", 313 "IOBRD0_PWR_GOOD-I","", 314 "","", 315 "","", 316 "FAN_FAIL_IN_L-I","", 317 "","", 318 "","", 319 "","", 320 "PDB_CABLE_PRESENT_L-I","", 321 "","", 322 "CHASSIS_PWR_BRK_L-I","", 323 "","", 324 "IOBRD1_IOX_INT_L-I","", 325 "10GBE_SMBALRT_L-I","", 326 "PCIE_WAKE_L-I","", 327 "I2C_M21_ALERT_L-I","", 328 "I2C_M20_ALERT_L-I","", 329 "TRAY_FAST_SHDN_L-I","", 330 "UID_BTN_N-I","", 331 "PWR_BTN_L-I","", 332 "PSU_SMB_ALERT_L-I","", 333 "","", 334 "","", 335 "NODE_LOC_ID[0]-I","", 336 "NODE_LOC_ID[1]-I","", 337 "NODE_LOC_ID[2]-I","", 338 "NODE_LOC_ID[3]-I","", 339 "NODE_LOC_ID[4]-I","", 340 "NODE_LOC_ID[5]-I","", 341 "FAN10_PRESENT_L-I","", 342 "FAN9_PRESENT_L-I","", 343 "FAN8_PRESENT_L-I","", 344 "FPGA1_READY_HMC-I","", 345 "DP_HPD-I","", 346 "HMC_I2C3_FPGA_ALERT_L-I","", 347 "HMC_I2C2_FPGA_ALERT_L-I","", 348 "FPGA0_READY_HMC-I","", 349 "","", 350 "","", 351 "","", 352 "","", 353 "LEAK_DETECT_ALERT_L-I","", 354 "MOD1_B2B_CABLE_PRESENT_L-I","", 355 "MOD1_CLINK_CABLE_PRESENT_L-I","", 356 "FAN11_PRESENT_L-I","", 357 "","", 358 "","", 359 "","", 360 "","", 361 "","", 362 "","", 363 "","", 364 "","", 365 "","", 366 "","", 367 "","", 368 "","", 369 "","", 370 "","", 371 "","", 372 "","", 373 "RSVD_SGPIO_IN_CRC[0]","RSVD_SGPIO_O_CRC[7]", 374 "RSVD_SGPIO_IN_CRC[1]","RSVD_SGPIO_O_CRC[6]", 375 "RSVD_SGPIO_IN_CRC[2]","RSVD_SGPIO_O_CRC[5]", 376 "RSVD_SGPIO_IN_CRC[3]","RSVD_SGPIO_O_CRC[4]", 377 "RSVD_SGPIO_IN_CRC[4]","RSVD_SGPIO_O_CRC[3]", 378 "RSVD_SGPIO_IN_CRC[5]","RSVD_SGPIO_O_CRC[2]", 379 "RSVD_SGPIO_IN_CRC[6]","RSVD_SGPIO_O_CRC[1]", 380 "RSVD_SGPIO_IN_CRC[7]","RSVD_SGPIO_O_CRC[0]"; 381}; 382 383// I2C1, SSIF IPMI interface 384&i2c0 { 385 status = "okay"; 386 clock-frequency = <400000>; 387 388 ssif-bmc@10 { 389 compatible = "ssif-bmc"; 390 reg = <0x10>; 391 }; 392}; 393 394// I2C2 395// BMC_I2C1_FPGA - Secondary FPGA 396// HMC EROT 397&i2c1 { 398 status = "okay"; 399 clock-frequency = <400000>; 400 multi-master; 401}; 402 403// I2C3 404// BMC_I2C0_FPGA - Primary FPGA 405// HMC FRU EEPROM 406&i2c2 { 407 status = "okay"; 408 clock-frequency = <400000>; 409 multi-master; 410}; 411 412// I2C4 413&i2c3 { 414 status = "disabled"; 415}; 416 417// I2C5 418// RTC Driver 419// IO Expander 420&i2c4 { 421 status = "okay"; 422 clock-frequency = <400000>; 423 424 // Module 0, Expander @0x21 425 exp4: gpio@21 { 426 compatible = "nxp,pca9555"; 427 reg = <0x21>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 interrupt-parent = <&gpio1>; 433 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 434 gpio-line-names = 435 "RTC_MUX_SEL-O", 436 "PCI_MUX_SEL-O", 437 "TPM_MUX_SEL-O", 438 "FAN_MUX-SEL-O", 439 "SGMII_MUX_SEL-O", 440 "DP_MUX_SEL-O", 441 "UPHY3_USB_SEL-O", 442 "NCSI_MUX_SEL-O", 443 "BMC_PHY_RST-O", 444 "RTC_CLR_L-O", 445 "BMC_12V_CTRL-O", 446 "PS_RUN_IO0_PG-I", 447 "", 448 "", 449 "", 450 ""; 451 }; 452}; 453 454// I2C6 455// Module 0/1 I2C MUX x3 456&i2c5 { 457 status = "okay"; 458 clock-frequency = <400000>; 459 multi-master; 460 461 i2c-mux@71 { 462 compatible = "nxp,pca9546"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <0x71>; 466 i2c-mux-idle-disconnect; 467 468 imux16: i2c@0 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <0>; 472 }; 473 474 imux17: i2c@1 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <1>; 478 479 i2c-mux@74 { 480 compatible = "nxp,pca9546"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <0x74>; 484 i2c-mux-idle-disconnect; 485 486 i2c17mux0: i2c@0 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 reg = <0>; 490 }; 491 492 i2c17mux1: i2c@1 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <1>; 496 }; 497 498 i2c17mux2: i2c@2 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <2>; 502 }; 503 504 i2c17mux3: i2c@3 { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 reg = <3>; 508 }; 509 }; 510 }; 511 512 imux18: i2c@2 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <2>; 516 }; 517 518 imux19: i2c@3 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 reg = <3>; 522 }; 523 }; 524 525 i2c-mux@72 { 526 compatible = "nxp,pca9546"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0x72>; 530 i2c-mux-idle-disconnect; 531 532 imux20: i2c@0 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0>; 536 }; 537 538 imux21: i2c@1 { 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <1>; 542 543 gpio@21 { 544 compatible = "nxp,pca9555"; 545 reg = <0x21>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 gpio-line-names = 549 "RST_CX_0_L-O", 550 "RST_CX_1_L-O", 551 "CX0_SSD0_PRSNT_L-I", 552 "CX1_SSD1_PRSNT_L-I", 553 "CX_BOOT_CMPLT_CX0-I", 554 "CX_BOOT_CMPLT_CX1-I", 555 "CX_TWARN_CX0_L-I", 556 "CX_TWARN_CX1_L-I", 557 "CX_OVT_SHDN_CX0-I", 558 "CX_OVT_SHDN_CX1-I", 559 "FNP_L_CX0-O", 560 "FNP_L_CX1-O", 561 "", 562 "MCU_GPIO-I", 563 "MCU_RST_N-O", 564 "MCU_RECOVERY_N-O"; 565 }; 566 }; 567 568 imux22: i2c@2 { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 reg = <2>; 572 }; 573 574 imux23: i2c@3 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <3>; 578 }; 579 }; 580 581 i2c-mux@73 { 582 compatible = "nxp,pca9546"; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 reg = <0x73>; 586 i2c-mux-idle-disconnect; 587 588 imux24: i2c@0 { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 reg = <0>; 592 }; 593 594 imux25: i2c@1 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 reg = <1>; 598 599 i2c-mux@70 { 600 compatible = "nxp,pca9546"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0x70>; 604 i2c-mux-idle-disconnect; 605 606 i2c25mux0: i2c@0 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 reg = <0>; 610 }; 611 612 i2c25mux1: i2c@1 { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 reg = <1>; 616 }; 617 618 i2c25mux2: i2c@2 { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 reg = <2>; 622 }; 623 624 i2c25mux3: i2c@3 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 reg = <3>; 628 }; 629 }; 630 }; 631 632 imux26: i2c@2 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <2>; 636 }; 637 638 imux27: i2c@3 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 reg = <3>; 642 }; 643 }; 644 645 i2c-mux@75 { 646 compatible = "nxp,pca9546"; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 reg = <0x75>; 650 i2c-mux-idle-disconnect; 651 652 imux28: i2c@0 { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 reg = <0>; 656 }; 657 658 imux29: i2c@1 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 reg = <1>; 662 663 i2c-mux@74 { 664 compatible = "nxp,pca9546"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 reg = <0x74>; 668 i2c-mux-idle-disconnect; 669 670 i2c29mux0: i2c@0 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 reg = <0>; 674 }; 675 676 i2c29mux1: i2c@1 { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 reg = <1>; 680 }; 681 682 i2c29mux2: i2c@2 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 reg = <2>; 686 }; 687 688 i2c29mux3: i2c@3 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 reg = <3>; 692 }; 693 }; 694 }; 695 696 imux30: i2c@2 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 reg = <2>; 700 }; 701 702 imux31: i2c@3 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 reg = <3>; 706 }; 707 }; 708 709 i2c-mux@76 { 710 compatible = "nxp,pca9546"; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 reg = <0x76>; 714 i2c-mux-idle-disconnect; 715 716 imux32: i2c@0 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 reg = <0>; 720 }; 721 722 imux33: i2c@1 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 reg = <1>; 726 727 gpio@21 { 728 compatible = "nxp,pca9555"; 729 reg = <0x21>; 730 gpio-controller; 731 #gpio-cells = <2>; 732 gpio-line-names = 733 "SEC_RST_CX_0_L-O", 734 "SEC_RST_CX_1_L-O", 735 "SEC_CX0_SSD0_PRSNT_L-I", 736 "SEC_CX1_SSD1_PRSNT_L-I", 737 "SEC_CX_BOOT_CMPLT_CX0-I", 738 "SEC_CX_BOOT_CMPLT_CX1-I", 739 "SEC_CX_TWARN_CX0_L-I", 740 "SEC_CX_TWARN_CX1_L-I", 741 "SEC_CX_OVT_SHDN_CX0-I", 742 "SEC_CX_OVT_SHDN_CX1-I", 743 "SEC_FNP_L_CX0-O", 744 "SEC_FNP_L_CX1-O", 745 "", 746 "SEC_MCU_GPIO-I", 747 "SEC_MCU_RST_N-O", 748 "SEC_MCU_RECOVERY_N-O"; 749 }; 750 }; 751 752 imux34: i2c@2 { 753 #address-cells = <1>; 754 #size-cells = <0>; 755 reg = <2>; 756 }; 757 758 imux35: i2c@3 { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 reg = <3>; 762 }; 763 }; 764 765 i2c-mux@77 { 766 compatible = "nxp,pca9546"; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 reg = <0x77>; 770 i2c-mux-idle-disconnect; 771 772 imux36: i2c@0 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 reg = <0>; 776 }; 777 778 imux37: i2c@1 { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 reg = <1>; 782 }; 783 784 imux38: i2c@2 { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 reg = <2>; 788 }; 789 790 imux39: i2c@3 { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 reg = <3>; 794 }; 795 }; 796}; 797 798// I2C7 799// Module 0/1 Leak Sensors 800// Module 0/1 Fan Controllers 801&i2c6 { 802 status = "okay"; 803 clock-frequency = <400000>; 804 805 pmic@12 { 806 compatible = "ti,lm5066i"; 807 reg = <0x12>; 808 shunt-resistor-micro-ohms = <190>; 809 status = "okay"; 810 }; 811 812 pmic@14 { 813 compatible = "ti,lm5066i"; 814 reg = <0x14>; 815 shunt-resistor-micro-ohms = <190>; 816 status = "okay"; 817 }; 818 819 pwm@20 { 820 compatible = "maxim,max31790"; 821 reg = <0x20>; 822 }; 823 824 pwm@23 { 825 compatible = "maxim,max31790"; 826 reg = <0x23>; 827 }; 828 829 pwm@2c { 830 compatible = "maxim,max31790"; 831 reg = <0x2c>; 832 }; 833 834 pwm@2f { 835 compatible = "maxim,max31790"; 836 reg = <0x2f>; 837 }; 838}; 839 840// I2C9 841// M.2 842&i2c8 { 843 status = "okay"; 844 clock-frequency = <400000>; 845 multi-master; 846}; 847 848// I2C10 849// HMC IO Expander 850// Module 0/1 IO Expanders 851&i2c9 { 852 status = "okay"; 853 clock-frequency = <400000>; 854 855 // Module 0, Expander @0x20 856 exp0: gpio@20 { 857 compatible = "nxp,pca9555"; 858 reg = <0x20>; 859 gpio-controller; 860 #gpio-cells = <2>; 861 interrupt-controller; 862 #interrupt-cells = <2>; 863 interrupt-parent = <&gpio1>; 864 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 865 gpio-line-names = 866 "FPGA_THERM_OVERT_L-I", 867 "FPGA_READY_BMC-I", 868 "HMC_BMC_DETECT-O", 869 "HMC_PGOOD-O", 870 "", 871 "BMC_STBY_CYCLE-O", 872 "FPGA_EROT_FATAL_ERROR_L-I", 873 "WP_HW_EXT_CTRL_L-O", 874 "EROT_FPGA_RST_L-O", 875 "FPGA_EROT_RECOVERY_L-O", 876 "BMC_EROT_FPGA_SPI_MUX_SEL-O", 877 "USB_HUB_RESET_L-O", 878 "NCSI_CS1_SEL-O", 879 "SGPIO_EN_L-O", 880 "B2B_IOEXP_INT_L-I", 881 "I2C_BUS_MUX_RESET_L-O"; 882 }; 883 884 // Module 1, Expander @0x21 885 exp1: gpio@21 { 886 compatible = "nxp,pca9555"; 887 reg = <0x21>; 888 gpio-controller; 889 #gpio-cells = <2>; 890 interrupt-controller; 891 #interrupt-cells = <2>; 892 interrupt-parent = <&gpio1>; 893 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 894 gpio-line-names = 895 "SEC_FPGA_THERM_OVERT_L-I", 896 "SEC_FPGA_READY_BMC-I", 897 "", 898 "", 899 "", 900 "", 901 "SEC_FPGA_EROT_FATAL_ERROR_L-I", 902 "SEC_WP_HW_EXT_CTRL_L-O", 903 "SEC_EROT_FPGA_RST_L-O", 904 "SEC_FPGA_EROT_RECOVERY_L-O", 905 "SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O", 906 "SEC_USB2_HUB_RST_L-O", 907 "", 908 "", 909 "", 910 "SEC_I2C_BUS_MUX_RESET_L-O"; 911 }; 912 913 // HMC Expander @0x27 914 exp2: gpio@27 { 915 compatible = "nxp,pca9555"; 916 reg = <0x27>; 917 gpio-controller; 918 #gpio-cells = <2>; 919 interrupt-controller; 920 #interrupt-cells = <2>; 921 interrupt-parent = <&gpio1>; 922 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 923 gpio-line-names = 924 "HMC_PRSNT_L-I", 925 "HMC_READY-I", 926 "HMC_EROT_FATAL_ERROR_L-I", 927 "I2C_MUX_SEL-O", 928 "HMC_EROT_SPI_MUX_SEL-O", 929 "HMC_EROT_RECOVERY_L-O", 930 "HMC_EROT_RST_L-O", 931 "GLOBAL_WP_HMC-O", 932 "FPGA_RST_L-O", 933 "USB2_HUB_RST-O", 934 "CPU_UART_MUX_SEL-O", 935 "", 936 "", 937 "", 938 "", 939 ""; 940 }; 941 942 // HMC Expander @0x74 943 exp3: gpio@74 { 944 compatible = "nxp,pca9555"; 945 reg = <0x74>; 946 gpio-controller; 947 #gpio-cells = <2>; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 interrupt-parent = <&gpio1>; 951 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 952 gpio-line-names = 953 "IOB_PRSNT_L", 954 "IOB_DP_HPD", 955 "IOX_BMC_RESET", 956 "IOB_IOEXP_INT_L", 957 "IOB_UID_LED_L", 958 "IOB_UID_BTN_L", 959 "IOB_SYS_RST_BTN_L", 960 "IOB_PWR_LED_L", 961 "IOB_PWR_BTN_L", 962 "IOB_PHY_RST", 963 "CPLD_JTAG_MUX_SEL", 964 "", 965 "", 966 "", 967 "", 968 ""; 969 }; 970}; 971 972// I2C11 973// BMC FRU EEPROM 974// BMC Temp Sensor 975&i2c10 { 976 status = "okay"; 977 clock-frequency = <400000>; 978 979 // BMC FRU EEPROM - 256 bytes 980 eeprom@50 { 981 compatible = "atmel,24c02"; 982 reg = <0x50>; 983 pagesize = <8>; 984 }; 985}; 986 987// I2C12 988&i2c11 { 989 status = "disabled"; 990}; 991 992// I2C13 993&i2c12 { 994 status = "disabled"; 995}; 996 997// I2C14 998// Module 0 UPHY3 SMBus 999&i2c13 { 1000 status = "disabled"; 1001}; 1002 1003// I2C15 1004// Module 1 UPHY3 SMBus 1005&i2c14 { 1006 status = "okay"; 1007 clock-frequency = <100000>; 1008 multi-master; 1009 1010 //E1.S drive slot 0-3 1011 i2c-mux@77 { 1012 compatible = "nxp,pca9546"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 reg = <0x77>; 1016 i2c-mux-idle-disconnect; 1017 1018 e1si2c0: i2c@0 { 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 reg = <0>; 1022 }; 1023 1024 e1si2c1: i2c@1 { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 reg = <1>; 1028 }; 1029 1030 e1si2c2: i2c@2 { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 reg = <2>; 1034 }; 1035 1036 e1si2c3: i2c@3 { 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 reg = <3>; 1040 }; 1041 }; 1042}; 1043 1044// I2C16 1045&i2c15 { 1046 status = "okay"; 1047 clock-frequency = <100000>; 1048 multi-master; 1049 1050 //E1.S drive slot 4-7 1051 i2c-mux@77 { 1052 compatible = "nxp,pca9546"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 reg = <0x77>; 1056 i2c-mux-idle-disconnect; 1057 1058 e1si2c4: i2c@0 { 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 reg = <0>; 1062 }; 1063 1064 e1si2c5: i2c@1 { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 reg = <1>; 1068 }; 1069 1070 e1si2c6: i2c@2 { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 reg = <2>; 1074 }; 1075 1076 e1si2c7: i2c@3 { 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 reg = <3>; 1080 }; 1081 }; 1082}; 1083 1084&rng { 1085 status = "okay"; 1086}; 1087 1088&gpio0 { 1089 gpio-line-names = 1090 /*A0-A7*/ "", "", "", "", "", "", "", "", 1091 /*B0-B7*/ "", "", "", "", "", "", "", "", 1092 /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", 1093 /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", 1094 /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O", 1095 "", "", "", "SGPIO_BMC_EN-O", 1096 /*F0-F7*/ "", "", "", "", "", "", "", "", 1097 /*G0-G7*/ "", "", "", "", "", "", "", "", 1098 /*H0-H7*/ "", "", "", "", "", "", "", "", 1099 /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O", 1100 /*J0-J7*/ "", "", "", "", "", "", "", "", 1101 /*K0-K7*/ "", "", "", "", "", "", "", "", 1102 /*L0-L7*/ "", "", "", "", "", "", "", "", 1103 /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "HMC_RESET_L-O", "STBY_POWER_EN-O", 1104 "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", 1105 /*N0-N7*/ "", "", "", "", "", "", "", "", 1106 /*O0-O7*/ "", "", "", "", "", "", "", "", 1107 /*P0-P7*/ "", "", "", "", "", "", "", "", 1108 /*Q0-Q7*/ "", "", "", "", "", "", "", "", 1109 /*R0-R7*/ "", "", "", "", "", "", "", "", 1110 /*S0-S7*/ "", "", "", "", "", "", "", "", 1111 /*T0-T7*/ "", "", "", "", "", "", "", "", 1112 /*U0-U7*/ "", "", "", "", "", "", "", "", 1113 /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "", 1114 /*W0-W7*/ "", "", "", "", "", "", "", "", 1115 /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", 1116 /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", 1117 /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; 1118}; 1119 1120&gpio1 { 1121 /* 36 1.8V GPIOs */ 1122 gpio-line-names = 1123 /*A0-A7*/ "", "", "", "", "", "", "", "", 1124 /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", 1125 /*C0-C7*/ "", "", "", "", "", "", "", "", 1126 /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I", 1127 /*E0-E7*/ "", "", "", "", "", "", "", ""; 1128}; 1129