12b8d94f4SDelphine CC Chiu// SPDX-License-Identifier: GPL-2.0-or-later 22b8d94f4SDelphine CC Chiu// Copyright 2022 Facebook Inc. 32b8d94f4SDelphine CC Chiu 42b8d94f4SDelphine CC Chiu/dts-v1/; 52b8d94f4SDelphine CC Chiu#include "aspeed-g6.dtsi" 62b8d94f4SDelphine CC Chiu#include <dt-bindings/gpio/aspeed-gpio.h> 72b8d94f4SDelphine CC Chiu#include <dt-bindings/leds/leds-pca955x.h> 82b8d94f4SDelphine CC Chiu#include <dt-bindings/i2c/i2c.h> 92b8d94f4SDelphine CC Chiu 102b8d94f4SDelphine CC Chiu/ { 112b8d94f4SDelphine CC Chiu model = "Facebook Yosemite 4 BMC"; 122b8d94f4SDelphine CC Chiu compatible = "facebook,yosemite4-bmc", "aspeed,ast2600"; 132b8d94f4SDelphine CC Chiu 142b8d94f4SDelphine CC Chiu aliases { 152b8d94f4SDelphine CC Chiu serial4 = &uart5; 162b8d94f4SDelphine CC Chiu serial5 = &uart6; 172b8d94f4SDelphine CC Chiu serial6 = &uart7; 182b8d94f4SDelphine CC Chiu serial7 = &uart8; 192b8d94f4SDelphine CC Chiu serial8 = &uart9; 20932df9afSRicky CX Wu 21d8e460b7SRicky CX Wu i2c16 = &imux16; 22d8e460b7SRicky CX Wu i2c17 = &imux17; 23d8e460b7SRicky CX Wu i2c18 = &imux18; 24d8e460b7SRicky CX Wu i2c19 = &imux19; 25d8e460b7SRicky CX Wu i2c20 = &imux20; 26d8e460b7SRicky CX Wu i2c21 = &imux21; 27d8e460b7SRicky CX Wu i2c22 = &imux22; 28d8e460b7SRicky CX Wu i2c23 = &imux23; 2940542a3dSRicky CX Wu i2c24 = &imux24; 3040542a3dSRicky CX Wu i2c25 = &imux25; 3140542a3dSRicky CX Wu i2c26 = &imux26; 3240542a3dSRicky CX Wu i2c27 = &imux27; 33e1b6c120SRicky CX Wu i2c28 = &imux28; 34e1b6c120SRicky CX Wu i2c29 = &imux29; 359c4ce0cdSRicky CX Wu i2c30 = &imux30; 369c4ce0cdSRicky CX Wu i2c31 = &imux31; 37ca32ea32SRicky CX Wu i2c32 = &imux32; 38ca32ea32SRicky CX Wu i2c33 = &imux33; 39932df9afSRicky CX Wu i2c34 = &imux34; 40932df9afSRicky CX Wu i2c35 = &imux35; 412b8d94f4SDelphine CC Chiu }; 422b8d94f4SDelphine CC Chiu 432b8d94f4SDelphine CC Chiu chosen { 442b8d94f4SDelphine CC Chiu stdout-path = "serial4:57600n8"; 452b8d94f4SDelphine CC Chiu }; 462b8d94f4SDelphine CC Chiu 472b8d94f4SDelphine CC Chiu memory@80000000 { 482b8d94f4SDelphine CC Chiu device_type = "memory"; 492b8d94f4SDelphine CC Chiu reg = <0x80000000 0x80000000>; 502b8d94f4SDelphine CC Chiu }; 512b8d94f4SDelphine CC Chiu 522b8d94f4SDelphine CC Chiu iio-hwmon { 532b8d94f4SDelphine CC Chiu compatible = "iio-hwmon"; 542b8d94f4SDelphine CC Chiu io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, 552b8d94f4SDelphine CC Chiu <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, 56d943e59cSRicky CX Wu <&adc1 0>, <&adc1 1>, <&adc1 7>; 572b8d94f4SDelphine CC Chiu }; 58f8940d07SRicky CX Wu 59f8940d07SRicky CX Wu spi { 60f8940d07SRicky CX Wu compatible = "spi-gpio"; 61f8940d07SRicky CX Wu #address-cells = <1>; 62f8940d07SRicky CX Wu #size-cells = <0>; 63f8940d07SRicky CX Wu 64f8940d07SRicky CX Wu sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; 65f8940d07SRicky CX Wu mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; 66f8940d07SRicky CX Wu miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; 67f8940d07SRicky CX Wu cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; 68f8940d07SRicky CX Wu num-chipselects = <1>; 69f8940d07SRicky CX Wu 70f8940d07SRicky CX Wu tpm@0 { 71f8940d07SRicky CX Wu compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 72f8940d07SRicky CX Wu reg = <0>; 73f8940d07SRicky CX Wu spi-max-frequency = <33000000>; 74f8940d07SRicky CX Wu }; 75f8940d07SRicky CX Wu }; 762b8d94f4SDelphine CC Chiu}; 772b8d94f4SDelphine CC Chiu 782b8d94f4SDelphine CC Chiu&uart1 { 792b8d94f4SDelphine CC Chiu status = "okay"; 802b8d94f4SDelphine CC Chiu}; 812b8d94f4SDelphine CC Chiu 822b8d94f4SDelphine CC Chiu&uart2 { 832b8d94f4SDelphine CC Chiu status = "okay"; 842b8d94f4SDelphine CC Chiu}; 852b8d94f4SDelphine CC Chiu 862b8d94f4SDelphine CC Chiu&uart3 { 872b8d94f4SDelphine CC Chiu status = "okay"; 882b8d94f4SDelphine CC Chiu}; 892b8d94f4SDelphine CC Chiu 902b8d94f4SDelphine CC Chiu&uart4 { 912b8d94f4SDelphine CC Chiu status = "okay"; 922b8d94f4SDelphine CC Chiu}; 932b8d94f4SDelphine CC Chiu 942b8d94f4SDelphine CC Chiu&uart5 { 952b8d94f4SDelphine CC Chiu status = "okay"; 962b8d94f4SDelphine CC Chiu}; 972b8d94f4SDelphine CC Chiu 982b8d94f4SDelphine CC Chiu&uart6 { 992b8d94f4SDelphine CC Chiu status = "okay"; 1002b8d94f4SDelphine CC Chiu}; 1012b8d94f4SDelphine CC Chiu 1022b8d94f4SDelphine CC Chiu&uart7 { 1032b8d94f4SDelphine CC Chiu status = "okay"; 1042b8d94f4SDelphine CC Chiu}; 1052b8d94f4SDelphine CC Chiu 1062b8d94f4SDelphine CC Chiu&uart8 { 1072b8d94f4SDelphine CC Chiu status = "okay"; 1082b8d94f4SDelphine CC Chiu}; 1092b8d94f4SDelphine CC Chiu 1102b8d94f4SDelphine CC Chiu&uart9 { 1112b8d94f4SDelphine CC Chiu status = "okay"; 1122b8d94f4SDelphine CC Chiu}; 1132b8d94f4SDelphine CC Chiu 1142b8d94f4SDelphine CC Chiu&wdt1 { 1152b8d94f4SDelphine CC Chiu status = "okay"; 1162b8d94f4SDelphine CC Chiu pinctrl-names = "default"; 1172b8d94f4SDelphine CC Chiu pinctrl-0 = <&pinctrl_wdtrst1_default>; 1182b8d94f4SDelphine CC Chiu aspeed,reset-type = "soc"; 1192b8d94f4SDelphine CC Chiu aspeed,external-signal; 1202b8d94f4SDelphine CC Chiu aspeed,ext-push-pull; 1212b8d94f4SDelphine CC Chiu aspeed,ext-active-high; 1222b8d94f4SDelphine CC Chiu aspeed,ext-pulse-duration = <256>; 1232b8d94f4SDelphine CC Chiu}; 1242b8d94f4SDelphine CC Chiu 12510a2c836SRicky CX Wu&wdt2 { 12610a2c836SRicky CX Wu status = "okay"; 12710a2c836SRicky CX Wu pinctrl-names = "default"; 12810a2c836SRicky CX Wu pinctrl-0 = <&pinctrl_wdtrst2_default>; 12910a2c836SRicky CX Wu aspeed,reset-type = "system"; 13010a2c836SRicky CX Wu}; 13110a2c836SRicky CX Wu 1322b8d94f4SDelphine CC Chiu&mac2 { 1332b8d94f4SDelphine CC Chiu status = "okay"; 1342b8d94f4SDelphine CC Chiu pinctrl-names = "default"; 1352b8d94f4SDelphine CC Chiu pinctrl-0 = <&pinctrl_rmii3_default>; 1362b8d94f4SDelphine CC Chiu use-ncsi; 137d62399f6SKrzysztof Kozlowski mellanox,multi-host; 1382b8d94f4SDelphine CC Chiu}; 1392b8d94f4SDelphine CC Chiu 1402b8d94f4SDelphine CC Chiu&mac3 { 1412b8d94f4SDelphine CC Chiu status = "okay"; 1422b8d94f4SDelphine CC Chiu pinctrl-names = "default"; 1432b8d94f4SDelphine CC Chiu pinctrl-0 = <&pinctrl_rmii4_default>; 1442b8d94f4SDelphine CC Chiu use-ncsi; 145d62399f6SKrzysztof Kozlowski mellanox,multi-host; 1462b8d94f4SDelphine CC Chiu}; 1472b8d94f4SDelphine CC Chiu 1482b8d94f4SDelphine CC Chiu&fmc { 1492b8d94f4SDelphine CC Chiu status = "okay"; 1502b8d94f4SDelphine CC Chiu flash@0 { 1512b8d94f4SDelphine CC Chiu status = "okay"; 1522b8d94f4SDelphine CC Chiu m25p,fast-read; 1532b8d94f4SDelphine CC Chiu label = "bmc"; 1549e92515fSRicky CX Wu spi-tx-bus-width = <2>; 1559e92515fSRicky CX Wu spi-rx-bus-width = <2>; 1562b8d94f4SDelphine CC Chiu spi-max-frequency = <50000000>; 157a22ecb26SRicky CX Wu#include "openbmc-flash-layout-128.dtsi" 1582b8d94f4SDelphine CC Chiu }; 1592b8d94f4SDelphine CC Chiu flash@1 { 1602b8d94f4SDelphine CC Chiu status = "okay"; 1612b8d94f4SDelphine CC Chiu m25p,fast-read; 162*21ef6499SPatrick Williams label = "alt-bmc"; 1639e92515fSRicky CX Wu spi-tx-bus-width = <2>; 1649e92515fSRicky CX Wu spi-rx-bus-width = <2>; 1652b8d94f4SDelphine CC Chiu spi-max-frequency = <50000000>; 1662b8d94f4SDelphine CC Chiu }; 1672b8d94f4SDelphine CC Chiu}; 1682b8d94f4SDelphine CC Chiu 1692b8d94f4SDelphine CC Chiu&i2c0 { 1702b8d94f4SDelphine CC Chiu status = "okay"; 1712b8d94f4SDelphine CC Chiu mctp-controller; 1722b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 1732b8d94f4SDelphine CC Chiu multi-master; 1742b8d94f4SDelphine CC Chiu 1752b8d94f4SDelphine CC Chiu mctp@10 { 1762b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 1772b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 1782b8d94f4SDelphine CC Chiu }; 1792b8d94f4SDelphine CC Chiu 1802e720155SRicky CX Wu gpio@21 { 1812e720155SRicky CX Wu compatible = "nxp,pca9506"; 1822e720155SRicky CX Wu reg = <0x21>; 1832e720155SRicky CX Wu gpio-controller; 1842e720155SRicky CX Wu #gpio-cells = <2>; 1852e720155SRicky CX Wu }; 1862e720155SRicky CX Wu 1872e720155SRicky CX Wu gpio@22 { 1882e720155SRicky CX Wu compatible = "nxp,pca9506"; 1892e720155SRicky CX Wu reg = <0x22>; 1902e720155SRicky CX Wu gpio-controller; 1912e720155SRicky CX Wu #gpio-cells = <2>; 1922e720155SRicky CX Wu }; 1932e720155SRicky CX Wu 1942e720155SRicky CX Wu gpio@23 { 1952e720155SRicky CX Wu compatible = "nxp,pca9506"; 1962e720155SRicky CX Wu reg = <0x23>; 1972e720155SRicky CX Wu gpio-controller; 1982e720155SRicky CX Wu #gpio-cells = <2>; 1992e720155SRicky CX Wu }; 2002e720155SRicky CX Wu 2012e720155SRicky CX Wu gpio@24 { 2022e720155SRicky CX Wu compatible = "nxp,pca9506"; 2032e720155SRicky CX Wu reg = <0x24>; 2042e720155SRicky CX Wu gpio-controller; 2052e720155SRicky CX Wu #gpio-cells = <2>; 2062e720155SRicky CX Wu }; 2072e720155SRicky CX Wu 2082b8d94f4SDelphine CC Chiu power-sensor@40 { 2099b956060SRicky CX Wu compatible = "adi,adm1281"; 2102b8d94f4SDelphine CC Chiu reg = <0x40>; 2119b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 2122b8d94f4SDelphine CC Chiu }; 2132b8d94f4SDelphine CC Chiu}; 2142b8d94f4SDelphine CC Chiu 2152b8d94f4SDelphine CC Chiu&i2c1 { 2162b8d94f4SDelphine CC Chiu status = "okay"; 2172b8d94f4SDelphine CC Chiu mctp-controller; 2182b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 2192b8d94f4SDelphine CC Chiu multi-master; 2202b8d94f4SDelphine CC Chiu 2212b8d94f4SDelphine CC Chiu mctp@10 { 2222b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 2232b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 2242b8d94f4SDelphine CC Chiu }; 2252b8d94f4SDelphine CC Chiu 2262e720155SRicky CX Wu gpio@21 { 2272e720155SRicky CX Wu compatible = "nxp,pca9506"; 2282e720155SRicky CX Wu reg = <0x21>; 2292e720155SRicky CX Wu gpio-controller; 2302e720155SRicky CX Wu #gpio-cells = <2>; 2312e720155SRicky CX Wu }; 2322e720155SRicky CX Wu 2332e720155SRicky CX Wu gpio@22 { 2342e720155SRicky CX Wu compatible = "nxp,pca9506"; 2352e720155SRicky CX Wu reg = <0x22>; 2362e720155SRicky CX Wu gpio-controller; 2372e720155SRicky CX Wu #gpio-cells = <2>; 2382e720155SRicky CX Wu }; 2392e720155SRicky CX Wu 2402e720155SRicky CX Wu gpio@23 { 2412e720155SRicky CX Wu compatible = "nxp,pca9506"; 2422e720155SRicky CX Wu reg = <0x23>; 2432e720155SRicky CX Wu gpio-controller; 2442e720155SRicky CX Wu #gpio-cells = <2>; 2452e720155SRicky CX Wu }; 2462e720155SRicky CX Wu 2472e720155SRicky CX Wu gpio@24 { 2482e720155SRicky CX Wu compatible = "nxp,pca9506"; 2492e720155SRicky CX Wu reg = <0x24>; 2502e720155SRicky CX Wu gpio-controller; 2512e720155SRicky CX Wu #gpio-cells = <2>; 2522e720155SRicky CX Wu }; 2532e720155SRicky CX Wu 2542b8d94f4SDelphine CC Chiu power-sensor@40 { 2559b956060SRicky CX Wu compatible = "adi,adm1281"; 2562b8d94f4SDelphine CC Chiu reg = <0x40>; 2579b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 2582b8d94f4SDelphine CC Chiu }; 2592b8d94f4SDelphine CC Chiu}; 2602b8d94f4SDelphine CC Chiu 2612b8d94f4SDelphine CC Chiu&i2c2 { 2622b8d94f4SDelphine CC Chiu status = "okay"; 2632b8d94f4SDelphine CC Chiu mctp-controller; 2642b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 2652b8d94f4SDelphine CC Chiu multi-master; 2662b8d94f4SDelphine CC Chiu 2672b8d94f4SDelphine CC Chiu mctp@10 { 2682b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 2692b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 2702b8d94f4SDelphine CC Chiu }; 2712b8d94f4SDelphine CC Chiu 2722e720155SRicky CX Wu gpio@21 { 2732e720155SRicky CX Wu compatible = "nxp,pca9506"; 2742e720155SRicky CX Wu reg = <0x21>; 2752e720155SRicky CX Wu gpio-controller; 2762e720155SRicky CX Wu #gpio-cells = <2>; 2772e720155SRicky CX Wu }; 2782e720155SRicky CX Wu 2792e720155SRicky CX Wu gpio@22 { 2802e720155SRicky CX Wu compatible = "nxp,pca9506"; 2812e720155SRicky CX Wu reg = <0x22>; 2822e720155SRicky CX Wu gpio-controller; 2832e720155SRicky CX Wu #gpio-cells = <2>; 2842e720155SRicky CX Wu }; 2852e720155SRicky CX Wu 2862e720155SRicky CX Wu gpio@23 { 2872e720155SRicky CX Wu compatible = "nxp,pca9506"; 2882e720155SRicky CX Wu reg = <0x23>; 2892e720155SRicky CX Wu gpio-controller; 2902e720155SRicky CX Wu #gpio-cells = <2>; 2912e720155SRicky CX Wu }; 2922e720155SRicky CX Wu 2932e720155SRicky CX Wu gpio@24 { 2942e720155SRicky CX Wu compatible = "nxp,pca9506"; 2952e720155SRicky CX Wu reg = <0x24>; 2962e720155SRicky CX Wu gpio-controller; 2972e720155SRicky CX Wu #gpio-cells = <2>; 2982e720155SRicky CX Wu }; 2992e720155SRicky CX Wu 3002b8d94f4SDelphine CC Chiu power-sensor@40 { 3019b956060SRicky CX Wu compatible = "adi,adm1281"; 3022b8d94f4SDelphine CC Chiu reg = <0x40>; 3039b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 3042b8d94f4SDelphine CC Chiu }; 3052b8d94f4SDelphine CC Chiu}; 3062b8d94f4SDelphine CC Chiu 3072b8d94f4SDelphine CC Chiu&i2c3 { 3082b8d94f4SDelphine CC Chiu status = "okay"; 3092b8d94f4SDelphine CC Chiu mctp-controller; 3102b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 3112b8d94f4SDelphine CC Chiu multi-master; 3122b8d94f4SDelphine CC Chiu 3132b8d94f4SDelphine CC Chiu mctp@10 { 3142b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 3152b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 3162b8d94f4SDelphine CC Chiu }; 3172b8d94f4SDelphine CC Chiu 3182e720155SRicky CX Wu gpio@21 { 3192e720155SRicky CX Wu compatible = "nxp,pca9506"; 3202e720155SRicky CX Wu reg = <0x21>; 3212e720155SRicky CX Wu gpio-controller; 3222e720155SRicky CX Wu #gpio-cells = <2>; 3232e720155SRicky CX Wu }; 3242e720155SRicky CX Wu 3252e720155SRicky CX Wu gpio@22 { 3262e720155SRicky CX Wu compatible = "nxp,pca9506"; 3272e720155SRicky CX Wu reg = <0x22>; 3282e720155SRicky CX Wu gpio-controller; 3292e720155SRicky CX Wu #gpio-cells = <2>; 3302e720155SRicky CX Wu }; 3312e720155SRicky CX Wu 3322e720155SRicky CX Wu gpio@23 { 3332e720155SRicky CX Wu compatible = "nxp,pca9506"; 3342e720155SRicky CX Wu reg = <0x23>; 3352e720155SRicky CX Wu gpio-controller; 3362e720155SRicky CX Wu #gpio-cells = <2>; 3372e720155SRicky CX Wu }; 3382e720155SRicky CX Wu 3392e720155SRicky CX Wu gpio@24 { 3402e720155SRicky CX Wu compatible = "nxp,pca9506"; 3412e720155SRicky CX Wu reg = <0x24>; 3422e720155SRicky CX Wu gpio-controller; 3432e720155SRicky CX Wu #gpio-cells = <2>; 3442e720155SRicky CX Wu }; 3452e720155SRicky CX Wu 3462b8d94f4SDelphine CC Chiu power-sensor@40 { 3479b956060SRicky CX Wu compatible = "adi,adm1281"; 3482b8d94f4SDelphine CC Chiu reg = <0x40>; 3499b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 3502b8d94f4SDelphine CC Chiu }; 3512b8d94f4SDelphine CC Chiu}; 3522b8d94f4SDelphine CC Chiu 3532b8d94f4SDelphine CC Chiu&i2c4 { 3542b8d94f4SDelphine CC Chiu status = "okay"; 3552b8d94f4SDelphine CC Chiu mctp-controller; 3562b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 3572b8d94f4SDelphine CC Chiu multi-master; 3582b8d94f4SDelphine CC Chiu 3592b8d94f4SDelphine CC Chiu mctp@10 { 3602b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 3612b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 3622b8d94f4SDelphine CC Chiu }; 3632b8d94f4SDelphine CC Chiu 3642e720155SRicky CX Wu gpio@21 { 3652e720155SRicky CX Wu compatible = "nxp,pca9506"; 3662e720155SRicky CX Wu reg = <0x21>; 3672e720155SRicky CX Wu gpio-controller; 3682e720155SRicky CX Wu #gpio-cells = <2>; 3692e720155SRicky CX Wu }; 3702e720155SRicky CX Wu 3712e720155SRicky CX Wu gpio@22 { 3722e720155SRicky CX Wu compatible = "nxp,pca9506"; 3732e720155SRicky CX Wu reg = <0x22>; 3742e720155SRicky CX Wu gpio-controller; 3752e720155SRicky CX Wu #gpio-cells = <2>; 3762e720155SRicky CX Wu }; 3772e720155SRicky CX Wu 3782e720155SRicky CX Wu gpio@23 { 3792e720155SRicky CX Wu compatible = "nxp,pca9506"; 3802e720155SRicky CX Wu reg = <0x23>; 3812e720155SRicky CX Wu gpio-controller; 3822e720155SRicky CX Wu #gpio-cells = <2>; 3832e720155SRicky CX Wu }; 3842e720155SRicky CX Wu 3852e720155SRicky CX Wu gpio@24 { 3862e720155SRicky CX Wu compatible = "nxp,pca9506"; 3872e720155SRicky CX Wu reg = <0x24>; 3882e720155SRicky CX Wu gpio-controller; 3892e720155SRicky CX Wu #gpio-cells = <2>; 3902e720155SRicky CX Wu }; 3912e720155SRicky CX Wu 3922b8d94f4SDelphine CC Chiu power-sensor@40 { 3939b956060SRicky CX Wu compatible = "adi,adm1281"; 3942b8d94f4SDelphine CC Chiu reg = <0x40>; 3959b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 3962b8d94f4SDelphine CC Chiu }; 3972b8d94f4SDelphine CC Chiu}; 3982b8d94f4SDelphine CC Chiu 3992b8d94f4SDelphine CC Chiu&i2c5 { 4002b8d94f4SDelphine CC Chiu status = "okay"; 4012b8d94f4SDelphine CC Chiu mctp-controller; 4022b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 4032b8d94f4SDelphine CC Chiu multi-master; 4042b8d94f4SDelphine CC Chiu 4052b8d94f4SDelphine CC Chiu mctp@10 { 4062b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 4072b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 4082b8d94f4SDelphine CC Chiu }; 4092b8d94f4SDelphine CC Chiu 4102e720155SRicky CX Wu gpio@21 { 4112e720155SRicky CX Wu compatible = "nxp,pca9506"; 4122e720155SRicky CX Wu reg = <0x21>; 4132e720155SRicky CX Wu gpio-controller; 4142e720155SRicky CX Wu #gpio-cells = <2>; 4152e720155SRicky CX Wu }; 4162e720155SRicky CX Wu 4172e720155SRicky CX Wu gpio@22 { 4182e720155SRicky CX Wu compatible = "nxp,pca9506"; 4192e720155SRicky CX Wu reg = <0x22>; 4202e720155SRicky CX Wu gpio-controller; 4212e720155SRicky CX Wu #gpio-cells = <2>; 4222e720155SRicky CX Wu }; 4232e720155SRicky CX Wu 4242e720155SRicky CX Wu gpio@23 { 4252e720155SRicky CX Wu compatible = "nxp,pca9506"; 4262e720155SRicky CX Wu reg = <0x23>; 4272e720155SRicky CX Wu gpio-controller; 4282e720155SRicky CX Wu #gpio-cells = <2>; 4292e720155SRicky CX Wu }; 4302e720155SRicky CX Wu 4312e720155SRicky CX Wu gpio@24 { 4322e720155SRicky CX Wu compatible = "nxp,pca9506"; 4332e720155SRicky CX Wu reg = <0x24>; 4342e720155SRicky CX Wu gpio-controller; 4352e720155SRicky CX Wu #gpio-cells = <2>; 4362e720155SRicky CX Wu }; 4372e720155SRicky CX Wu 4382b8d94f4SDelphine CC Chiu power-sensor@40 { 4399b956060SRicky CX Wu compatible = "adi,adm1281"; 4402b8d94f4SDelphine CC Chiu reg = <0x40>; 4419b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 4422b8d94f4SDelphine CC Chiu }; 4432b8d94f4SDelphine CC Chiu}; 4442b8d94f4SDelphine CC Chiu 4452b8d94f4SDelphine CC Chiu&i2c6 { 4462b8d94f4SDelphine CC Chiu status = "okay"; 4472b8d94f4SDelphine CC Chiu mctp-controller; 4482b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 4492b8d94f4SDelphine CC Chiu multi-master; 4502b8d94f4SDelphine CC Chiu 4512b8d94f4SDelphine CC Chiu mctp@10 { 4522b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 4532b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 4542b8d94f4SDelphine CC Chiu }; 4552b8d94f4SDelphine CC Chiu 4562e720155SRicky CX Wu gpio@21 { 4572e720155SRicky CX Wu compatible = "nxp,pca9506"; 4582e720155SRicky CX Wu reg = <0x21>; 4592e720155SRicky CX Wu gpio-controller; 4602e720155SRicky CX Wu #gpio-cells = <2>; 4612e720155SRicky CX Wu }; 4622e720155SRicky CX Wu 4632e720155SRicky CX Wu gpio@22 { 4642e720155SRicky CX Wu compatible = "nxp,pca9506"; 4652e720155SRicky CX Wu reg = <0x22>; 4662e720155SRicky CX Wu gpio-controller; 4672e720155SRicky CX Wu #gpio-cells = <2>; 4682e720155SRicky CX Wu }; 4692e720155SRicky CX Wu 4702e720155SRicky CX Wu gpio@23 { 4712e720155SRicky CX Wu compatible = "nxp,pca9506"; 4722e720155SRicky CX Wu reg = <0x23>; 4732e720155SRicky CX Wu gpio-controller; 4742e720155SRicky CX Wu #gpio-cells = <2>; 4752e720155SRicky CX Wu }; 4762e720155SRicky CX Wu 4772e720155SRicky CX Wu gpio@24 { 4782e720155SRicky CX Wu compatible = "nxp,pca9506"; 4792e720155SRicky CX Wu reg = <0x24>; 4802e720155SRicky CX Wu gpio-controller; 4812e720155SRicky CX Wu #gpio-cells = <2>; 4822e720155SRicky CX Wu }; 4832e720155SRicky CX Wu 4842b8d94f4SDelphine CC Chiu power-sensor@40 { 4859b956060SRicky CX Wu compatible = "adi,adm1281"; 4862b8d94f4SDelphine CC Chiu reg = <0x40>; 4879b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 4882b8d94f4SDelphine CC Chiu }; 4892b8d94f4SDelphine CC Chiu}; 4902b8d94f4SDelphine CC Chiu 4912b8d94f4SDelphine CC Chiu&i2c7 { 4922b8d94f4SDelphine CC Chiu status = "okay"; 4932b8d94f4SDelphine CC Chiu mctp-controller; 4942b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 4952b8d94f4SDelphine CC Chiu multi-master; 4962b8d94f4SDelphine CC Chiu 4972b8d94f4SDelphine CC Chiu mctp@10 { 4982b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 4992b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 5002b8d94f4SDelphine CC Chiu }; 5012b8d94f4SDelphine CC Chiu 5022e720155SRicky CX Wu gpio@21 { 5032e720155SRicky CX Wu compatible = "nxp,pca9506"; 5042e720155SRicky CX Wu reg = <0x21>; 5052e720155SRicky CX Wu gpio-controller; 5062e720155SRicky CX Wu #gpio-cells = <2>; 5072e720155SRicky CX Wu }; 5082e720155SRicky CX Wu 5092e720155SRicky CX Wu gpio@22 { 5102e720155SRicky CX Wu compatible = "nxp,pca9506"; 5112e720155SRicky CX Wu reg = <0x22>; 5122e720155SRicky CX Wu gpio-controller; 5132e720155SRicky CX Wu #gpio-cells = <2>; 5142e720155SRicky CX Wu }; 5152e720155SRicky CX Wu 5162e720155SRicky CX Wu gpio@23 { 5172e720155SRicky CX Wu compatible = "nxp,pca9506"; 5182e720155SRicky CX Wu reg = <0x23>; 5192e720155SRicky CX Wu gpio-controller; 5202e720155SRicky CX Wu #gpio-cells = <2>; 5212e720155SRicky CX Wu }; 5222e720155SRicky CX Wu 5232e720155SRicky CX Wu gpio@24 { 5242e720155SRicky CX Wu compatible = "nxp,pca9506"; 5252e720155SRicky CX Wu reg = <0x24>; 5262e720155SRicky CX Wu gpio-controller; 5272e720155SRicky CX Wu #gpio-cells = <2>; 5282e720155SRicky CX Wu }; 5292e720155SRicky CX Wu 5302b8d94f4SDelphine CC Chiu power-sensor@40 { 5319b956060SRicky CX Wu compatible = "adi,adm1281"; 5322b8d94f4SDelphine CC Chiu reg = <0x40>; 5339b956060SRicky CX Wu shunt-resistor-micro-ohms = <500>; 5342b8d94f4SDelphine CC Chiu }; 5352b8d94f4SDelphine CC Chiu}; 5362b8d94f4SDelphine CC Chiu 5372b8d94f4SDelphine CC Chiu&i2c8 { 538d8e460b7SRicky CX Wu #address-cells = <1>; 539d8e460b7SRicky CX Wu #size-cells = <0>; 5402b8d94f4SDelphine CC Chiu status = "okay"; 5412b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 5422b8d94f4SDelphine CC Chiu i2c-mux@70 { 5432b8d94f4SDelphine CC Chiu compatible = "nxp,pca9544"; 5442b8d94f4SDelphine CC Chiu reg = <0x70>; 545d8e460b7SRicky CX Wu #address-cells = <1>; 546d8e460b7SRicky CX Wu #size-cells = <0>; 547d8e460b7SRicky CX Wu i2c-mux-idle-disconnect; 548d8e460b7SRicky CX Wu 549d8e460b7SRicky CX Wu imux16: i2c@0 { 550d8e460b7SRicky CX Wu reg = <0>; 551d8e460b7SRicky CX Wu #address-cells = <1>; 552d8e460b7SRicky CX Wu #size-cells = <0>; 553d8e460b7SRicky CX Wu gpio@49 { 554d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 555d8e460b7SRicky CX Wu reg = <0x49>; 556d8e460b7SRicky CX Wu gpio-controller; 557d8e460b7SRicky CX Wu #gpio-cells = <2>; 558d8e460b7SRicky CX Wu }; 559d8e460b7SRicky CX Wu 560d8e460b7SRicky CX Wu eeprom@50 { 561d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 562d8e460b7SRicky CX Wu reg = <0x50>; 563d8e460b7SRicky CX Wu }; 564d8e460b7SRicky CX Wu 565d8e460b7SRicky CX Wu eeprom@51 { 566d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 567d8e460b7SRicky CX Wu reg = <0x51>; 568d8e460b7SRicky CX Wu }; 569d8e460b7SRicky CX Wu 570d8e460b7SRicky CX Wu eeprom@54 { 571d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 572d8e460b7SRicky CX Wu reg = <0x54>; 573d8e460b7SRicky CX Wu }; 574d8e460b7SRicky CX Wu }; 575d8e460b7SRicky CX Wu 576d8e460b7SRicky CX Wu imux17: i2c@1 { 577d8e460b7SRicky CX Wu reg = <1>; 578d8e460b7SRicky CX Wu #address-cells = <1>; 579d8e460b7SRicky CX Wu #size-cells = <0>; 580d8e460b7SRicky CX Wu gpio@49 { 581d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 582d8e460b7SRicky CX Wu reg = <0x49>; 583d8e460b7SRicky CX Wu gpio-controller; 584d8e460b7SRicky CX Wu #gpio-cells = <2>; 585d8e460b7SRicky CX Wu }; 586d8e460b7SRicky CX Wu 587d8e460b7SRicky CX Wu eeprom@50 { 588d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 589d8e460b7SRicky CX Wu reg = <0x50>; 590d8e460b7SRicky CX Wu }; 591d8e460b7SRicky CX Wu 592d8e460b7SRicky CX Wu eeprom@51 { 593d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 594d8e460b7SRicky CX Wu reg = <0x51>; 595d8e460b7SRicky CX Wu }; 596d8e460b7SRicky CX Wu 597d8e460b7SRicky CX Wu eeprom@54 { 598d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 599d8e460b7SRicky CX Wu reg = <0x54>; 600d8e460b7SRicky CX Wu }; 601d8e460b7SRicky CX Wu }; 602d8e460b7SRicky CX Wu 603d8e460b7SRicky CX Wu imux18: i2c@2 { 604d8e460b7SRicky CX Wu reg = <2>; 605d8e460b7SRicky CX Wu #address-cells = <1>; 606d8e460b7SRicky CX Wu #size-cells = <0>; 607d8e460b7SRicky CX Wu gpio@49 { 608d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 609d8e460b7SRicky CX Wu reg = <0x49>; 610d8e460b7SRicky CX Wu gpio-controller; 611d8e460b7SRicky CX Wu #gpio-cells = <2>; 612d8e460b7SRicky CX Wu }; 613d8e460b7SRicky CX Wu 614d8e460b7SRicky CX Wu eeprom@50 { 615d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 616d8e460b7SRicky CX Wu reg = <0x50>; 617d8e460b7SRicky CX Wu }; 618d8e460b7SRicky CX Wu 619d8e460b7SRicky CX Wu eeprom@51 { 620d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 621d8e460b7SRicky CX Wu reg = <0x51>; 622d8e460b7SRicky CX Wu }; 623d8e460b7SRicky CX Wu 624d8e460b7SRicky CX Wu eeprom@54 { 625d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 626d8e460b7SRicky CX Wu reg = <0x54>; 627d8e460b7SRicky CX Wu }; 628d8e460b7SRicky CX Wu }; 629d8e460b7SRicky CX Wu 630d8e460b7SRicky CX Wu imux19: i2c@3 { 631d8e460b7SRicky CX Wu reg = <3>; 632d8e460b7SRicky CX Wu #address-cells = <1>; 633d8e460b7SRicky CX Wu #size-cells = <0>; 634d8e460b7SRicky CX Wu gpio@49 { 635d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 636d8e460b7SRicky CX Wu reg = <0x49>; 637d8e460b7SRicky CX Wu gpio-controller; 638d8e460b7SRicky CX Wu #gpio-cells = <2>; 639d8e460b7SRicky CX Wu }; 640d8e460b7SRicky CX Wu 641d8e460b7SRicky CX Wu eeprom@50 { 642d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 643d8e460b7SRicky CX Wu reg = <0x50>; 644d8e460b7SRicky CX Wu }; 645d8e460b7SRicky CX Wu 646d8e460b7SRicky CX Wu eeprom@51 { 647d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 648d8e460b7SRicky CX Wu reg = <0x51>; 649d8e460b7SRicky CX Wu }; 650d8e460b7SRicky CX Wu 651d8e460b7SRicky CX Wu eeprom@54 { 652d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 653d8e460b7SRicky CX Wu reg = <0x54>; 654d8e460b7SRicky CX Wu }; 655d8e460b7SRicky CX Wu }; 6562b8d94f4SDelphine CC Chiu }; 6572b8d94f4SDelphine CC Chiu}; 6582b8d94f4SDelphine CC Chiu 6592b8d94f4SDelphine CC Chiu&i2c9 { 660d8e460b7SRicky CX Wu #address-cells = <1>; 661d8e460b7SRicky CX Wu #size-cells = <0>; 6622b8d94f4SDelphine CC Chiu status = "okay"; 6632b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 6642b8d94f4SDelphine CC Chiu i2c-mux@71 { 6652b8d94f4SDelphine CC Chiu compatible = "nxp,pca9544"; 6662b8d94f4SDelphine CC Chiu reg = <0x71>; 667d8e460b7SRicky CX Wu #address-cells = <1>; 668d8e460b7SRicky CX Wu #size-cells = <0>; 669d8e460b7SRicky CX Wu i2c-mux-idle-disconnect; 670d8e460b7SRicky CX Wu 671d8e460b7SRicky CX Wu imux20: i2c@0 { 672d8e460b7SRicky CX Wu reg = <0>; 673d8e460b7SRicky CX Wu #address-cells = <1>; 674d8e460b7SRicky CX Wu #size-cells = <0>; 675d8e460b7SRicky CX Wu gpio@49 { 676d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 677d8e460b7SRicky CX Wu reg = <0x49>; 678d8e460b7SRicky CX Wu gpio-controller; 679d8e460b7SRicky CX Wu #gpio-cells = <2>; 680d8e460b7SRicky CX Wu }; 681d8e460b7SRicky CX Wu 682d8e460b7SRicky CX Wu eeprom@50 { 683d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 684d8e460b7SRicky CX Wu reg = <0x50>; 685d8e460b7SRicky CX Wu }; 686d8e460b7SRicky CX Wu 687d8e460b7SRicky CX Wu eeprom@51 { 688d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 689d8e460b7SRicky CX Wu reg = <0x51>; 690d8e460b7SRicky CX Wu }; 691d8e460b7SRicky CX Wu 692d8e460b7SRicky CX Wu eeprom@54 { 693d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 694d8e460b7SRicky CX Wu reg = <0x54>; 695d8e460b7SRicky CX Wu }; 696d8e460b7SRicky CX Wu }; 697d8e460b7SRicky CX Wu 698d8e460b7SRicky CX Wu imux21: i2c@1 { 699d8e460b7SRicky CX Wu reg = <1>; 700d8e460b7SRicky CX Wu #address-cells = <1>; 701d8e460b7SRicky CX Wu #size-cells = <0>; 702d8e460b7SRicky CX Wu gpio@49 { 703d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 704d8e460b7SRicky CX Wu reg = <0x49>; 705d8e460b7SRicky CX Wu gpio-controller; 706d8e460b7SRicky CX Wu #gpio-cells = <2>; 707d8e460b7SRicky CX Wu }; 708d8e460b7SRicky CX Wu 709d8e460b7SRicky CX Wu eeprom@50 { 710d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 711d8e460b7SRicky CX Wu reg = <0x50>; 712d8e460b7SRicky CX Wu }; 713d8e460b7SRicky CX Wu 714d8e460b7SRicky CX Wu eeprom@51 { 715d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 716d8e460b7SRicky CX Wu reg = <0x51>; 717d8e460b7SRicky CX Wu }; 718d8e460b7SRicky CX Wu 719d8e460b7SRicky CX Wu eeprom@54 { 720d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 721d8e460b7SRicky CX Wu reg = <0x54>; 722d8e460b7SRicky CX Wu }; 723d8e460b7SRicky CX Wu }; 724d8e460b7SRicky CX Wu 725d8e460b7SRicky CX Wu imux22: i2c@2 { 726d8e460b7SRicky CX Wu reg = <2>; 727d8e460b7SRicky CX Wu #address-cells = <1>; 728d8e460b7SRicky CX Wu #size-cells = <0>; 729d8e460b7SRicky CX Wu gpio@49 { 730d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 731d8e460b7SRicky CX Wu reg = <0x49>; 732d8e460b7SRicky CX Wu gpio-controller; 733d8e460b7SRicky CX Wu #gpio-cells = <2>; 734d8e460b7SRicky CX Wu }; 735d8e460b7SRicky CX Wu 736d8e460b7SRicky CX Wu eeprom@50 { 737d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 738d8e460b7SRicky CX Wu reg = <0x50>; 739d8e460b7SRicky CX Wu }; 740d8e460b7SRicky CX Wu 741d8e460b7SRicky CX Wu eeprom@51 { 742d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 743d8e460b7SRicky CX Wu reg = <0x51>; 744d8e460b7SRicky CX Wu }; 745d8e460b7SRicky CX Wu 746d8e460b7SRicky CX Wu eeprom@54 { 747d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 748d8e460b7SRicky CX Wu reg = <0x54>; 749d8e460b7SRicky CX Wu }; 750d8e460b7SRicky CX Wu }; 751d8e460b7SRicky CX Wu 752d8e460b7SRicky CX Wu imux23: i2c@3 { 753d8e460b7SRicky CX Wu reg = <3>; 754d8e460b7SRicky CX Wu #address-cells = <1>; 755d8e460b7SRicky CX Wu #size-cells = <0>; 756d8e460b7SRicky CX Wu gpio@49 { 757d8e460b7SRicky CX Wu compatible = "nxp,pca9537"; 758d8e460b7SRicky CX Wu reg = <0x49>; 759d8e460b7SRicky CX Wu gpio-controller; 760d8e460b7SRicky CX Wu #gpio-cells = <2>; 761d8e460b7SRicky CX Wu }; 762d8e460b7SRicky CX Wu 763d8e460b7SRicky CX Wu eeprom@50 { 764d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 765d8e460b7SRicky CX Wu reg = <0x50>; 766d8e460b7SRicky CX Wu }; 767d8e460b7SRicky CX Wu 768d8e460b7SRicky CX Wu eeprom@51 { 769d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 770d8e460b7SRicky CX Wu reg = <0x51>; 771d8e460b7SRicky CX Wu }; 772d8e460b7SRicky CX Wu 773d8e460b7SRicky CX Wu eeprom@54 { 774d8e460b7SRicky CX Wu compatible = "atmel,24c128"; 775d8e460b7SRicky CX Wu reg = <0x54>; 776d8e460b7SRicky CX Wu }; 777d8e460b7SRicky CX Wu }; 7782b8d94f4SDelphine CC Chiu }; 7792b8d94f4SDelphine CC Chiu}; 7802b8d94f4SDelphine CC Chiu 7812b8d94f4SDelphine CC Chiu&i2c10 { 782e1b6c120SRicky CX Wu #address-cells = <1>; 783e1b6c120SRicky CX Wu #size-cells = <0>; 7842b8d94f4SDelphine CC Chiu status = "okay"; 7852b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 786e1b6c120SRicky CX Wu i2c-mux@74 { 787e1b6c120SRicky CX Wu compatible = "nxp,pca9544"; 788e1b6c120SRicky CX Wu reg = <0x74>; 789e1b6c120SRicky CX Wu #address-cells = <1>; 790e1b6c120SRicky CX Wu #size-cells = <0>; 791e1b6c120SRicky CX Wu i2c-mux-idle-disconnect; 792e1b6c120SRicky CX Wu 793e1b6c120SRicky CX Wu imux28: i2c@0 { 794e1b6c120SRicky CX Wu reg = <0>; 795e1b6c120SRicky CX Wu #address-cells = <1>; 796e1b6c120SRicky CX Wu #size-cells = <0>; 797e1b6c120SRicky CX Wu 798e1b6c120SRicky CX Wu gpio@20 { 799e1b6c120SRicky CX Wu compatible = "nxp,pca9506"; 800e1b6c120SRicky CX Wu reg = <0x20>; 801e1b6c120SRicky CX Wu gpio-controller; 802e1b6c120SRicky CX Wu #gpio-cells = <2>; 803e1b6c120SRicky CX Wu }; 804e1b6c120SRicky CX Wu 805e1b6c120SRicky CX Wu gpio@21 { 806e1b6c120SRicky CX Wu compatible = "nxp,pca9506"; 807e1b6c120SRicky CX Wu reg = <0x21>; 808e1b6c120SRicky CX Wu gpio-controller; 809e1b6c120SRicky CX Wu #gpio-cells = <2>; 810e1b6c120SRicky CX Wu }; 811e1b6c120SRicky CX Wu 812e1b6c120SRicky CX Wu gpio@22 { 813e1b6c120SRicky CX Wu compatible = "nxp,pca9506"; 814e1b6c120SRicky CX Wu reg = <0x22>; 815e1b6c120SRicky CX Wu gpio-controller; 816e1b6c120SRicky CX Wu #gpio-cells = <2>; 817e1b6c120SRicky CX Wu }; 818e1b6c120SRicky CX Wu 819e1b6c120SRicky CX Wu gpio@23 { 820e1b6c120SRicky CX Wu compatible = "nxp,pca9506"; 821e1b6c120SRicky CX Wu reg = <0x23>; 822e1b6c120SRicky CX Wu gpio-controller; 823e1b6c120SRicky CX Wu #gpio-cells = <2>; 824e1b6c120SRicky CX Wu }; 825e1b6c120SRicky CX Wu 826e1b6c120SRicky CX Wu gpio@24 { 827e1b6c120SRicky CX Wu compatible = "nxp,pca9506"; 828e1b6c120SRicky CX Wu reg = <0x24>; 829e1b6c120SRicky CX Wu gpio-controller; 830e1b6c120SRicky CX Wu #gpio-cells = <2>; 831e1b6c120SRicky CX Wu gpio-line-names = "","","","", 832e1b6c120SRicky CX Wu "NIC0_MAIN_PWR_EN", 833e1b6c120SRicky CX Wu "NIC1_MAIN_PWR_EN", 834e1b6c120SRicky CX Wu "NIC2_MAIN_PWR_EN", 835e1b6c120SRicky CX Wu "NIC3_MAIN_PWR_EN", 836e1b6c120SRicky CX Wu "","","","","","","","", 837e1b6c120SRicky CX Wu "","","","","","","","", 838e1b6c120SRicky CX Wu "","","","","","","",""; 839e1b6c120SRicky CX Wu }; 840e1b6c120SRicky CX Wu }; 841e1b6c120SRicky CX Wu 842e1b6c120SRicky CX Wu imux29: i2c@1 { 843e1b6c120SRicky CX Wu reg = <1>; 844e1b6c120SRicky CX Wu #address-cells = <1>; 845e1b6c120SRicky CX Wu #size-cells = <0>; 846e1b6c120SRicky CX Wu }; 847e1b6c120SRicky CX Wu }; 8482b8d94f4SDelphine CC Chiu}; 8492b8d94f4SDelphine CC Chiu 8502b8d94f4SDelphine CC Chiu&i2c11 { 8512b8d94f4SDelphine CC Chiu status = "okay"; 8522b8d94f4SDelphine CC Chiu power-sensor@10 { 8532b8d94f4SDelphine CC Chiu compatible = "adi,adm1272"; 8542b8d94f4SDelphine CC Chiu reg = <0x10>; 8552b8d94f4SDelphine CC Chiu }; 8562b8d94f4SDelphine CC Chiu 8572b8d94f4SDelphine CC Chiu power-sensor@12 { 8582b8d94f4SDelphine CC Chiu compatible = "adi,adm1272"; 8592b8d94f4SDelphine CC Chiu reg = <0x12>; 8602b8d94f4SDelphine CC Chiu }; 8612b8d94f4SDelphine CC Chiu 8622b8d94f4SDelphine CC Chiu gpio@20 { 8632b8d94f4SDelphine CC Chiu compatible = "nxp,pca9555"; 8642b8d94f4SDelphine CC Chiu reg = <0x20>; 8652b8d94f4SDelphine CC Chiu gpio-controller; 8662b8d94f4SDelphine CC Chiu #gpio-cells = <2>; 867bd9cac1eSRicky CX Wu interrupt-parent = <&gpio0>; 868bd9cac1eSRicky CX Wu interrupts = <98 IRQ_TYPE_LEVEL_LOW>; 869bd9cac1eSRicky CX Wu gpio-line-names = "P48V_OCP_GPIO1", "P48V_OCP_GPIO2", 870bd9cac1eSRicky CX Wu "P48V_OCP_GPIO3", "FAN_BOARD_0_REVISION_0_R", 871bd9cac1eSRicky CX Wu "FAN_BOARD_0_REVISION_1_R", 872bd9cac1eSRicky CX Wu "FAN_BOARD_1_REVISION_0_R", 873bd9cac1eSRicky CX Wu "FAN_BOARD_1_REVISION_1_R", "RST_MUX_R_N", 874bd9cac1eSRicky CX Wu "RST_LED_CONTROL_FAN_BOARD_0_N", 875bd9cac1eSRicky CX Wu "RST_LED_CONTROL_FAN_BOARD_1_N", 876bd9cac1eSRicky CX Wu "RST_IOEXP_FAN_BOARD_0_N", 877bd9cac1eSRicky CX Wu "RST_IOEXP_FAN_BOARD_1_N", 878bd9cac1eSRicky CX Wu "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R", 879bd9cac1eSRicky CX Wu "PWRGD_LOAD_SWITCH_FAN_BOARD_1_R", 880bd9cac1eSRicky CX Wu "", ""; 8812b8d94f4SDelphine CC Chiu }; 8822b8d94f4SDelphine CC Chiu 8832b8d94f4SDelphine CC Chiu gpio@21 { 8842b8d94f4SDelphine CC Chiu compatible = "nxp,pca9555"; 8852b8d94f4SDelphine CC Chiu reg = <0x21>; 8862b8d94f4SDelphine CC Chiu gpio-controller; 8872b8d94f4SDelphine CC Chiu #gpio-cells = <2>; 888bd9cac1eSRicky CX Wu interrupt-parent = <&gpio0>; 889bd9cac1eSRicky CX Wu interrupts = <98 IRQ_TYPE_LEVEL_LOW>; 890bd9cac1eSRicky CX Wu gpio-line-names = "HSC_OCP_SLOT_ODD_GPIO1", 891bd9cac1eSRicky CX Wu "HSC_OCP_SLOT_ODD_GPIO2", 892bd9cac1eSRicky CX Wu "HSC_OCP_SLOT_ODD_GPIO3", 893bd9cac1eSRicky CX Wu "HSC_OCP_SLOT_EVEN_GPIO1", 894bd9cac1eSRicky CX Wu "HSC_OCP_SLOT_EVEN_GPIO2", 895bd9cac1eSRicky CX Wu "HSC_OCP_SLOT_EVEN_GPIO3", 896bd9cac1eSRicky CX Wu "ADC_TYPE_0_R", "ADC_TYPE_1_R", 897bd9cac1eSRicky CX Wu "MEDUSA_BOARD_REV_0", "MEDUSA_BOARD_REV_1", 898bd9cac1eSRicky CX Wu "MEDUSA_BOARD_REV_2", "MEDUSA_BOARD_TYPE", 899bd9cac1eSRicky CX Wu "DELTA_MODULE_TYPE", "P12V_HSC_TYPE", 900bd9cac1eSRicky CX Wu "", ""; 9012b8d94f4SDelphine CC Chiu }; 9022b8d94f4SDelphine CC Chiu 9032b8d94f4SDelphine CC Chiu gpio@22 { 9042b8d94f4SDelphine CC Chiu compatible = "nxp,pca9555"; 9052b8d94f4SDelphine CC Chiu reg = <0x22>; 9062b8d94f4SDelphine CC Chiu gpio-controller; 9072b8d94f4SDelphine CC Chiu #gpio-cells = <2>; 908bd9cac1eSRicky CX Wu interrupt-parent = <&gpio0>; 909bd9cac1eSRicky CX Wu interrupts = <98 IRQ_TYPE_LEVEL_LOW>; 910bd9cac1eSRicky CX Wu gpio-line-names = "CARD_TYPE_SLOT1", "CARD_TYPE_SLOT2", 911bd9cac1eSRicky CX Wu "CARD_TYPE_SLOT3", "CARD_TYPE_SLOT4", 912bd9cac1eSRicky CX Wu "CARD_TYPE_SLOT5", "CARD_TYPE_SLOT6", 913bd9cac1eSRicky CX Wu "CARD_TYPE_SLOT7", "CARD_TYPE_SLOT8", 914bd9cac1eSRicky CX Wu "OC_P48V_HSC_0_N", "FLT_P48V_HSC_0_N", 915bd9cac1eSRicky CX Wu "OC_P48V_HSC_1_N", "FLT_P48V_HSC_1_N", 916bd9cac1eSRicky CX Wu "EN_P48V_AUX_0", "EN_P48V_AUX_1", 917bd9cac1eSRicky CX Wu "PWRGD_P12V_AUX_0", "PWRGD_P12V_AUX_1"; 9182b8d94f4SDelphine CC Chiu }; 9192b8d94f4SDelphine CC Chiu 9202b8d94f4SDelphine CC Chiu gpio@23 { 9212b8d94f4SDelphine CC Chiu compatible = "nxp,pca9555"; 9222b8d94f4SDelphine CC Chiu reg = <0x23>; 9232b8d94f4SDelphine CC Chiu gpio-controller; 9242b8d94f4SDelphine CC Chiu #gpio-cells = <2>; 925bd9cac1eSRicky CX Wu interrupt-parent = <&gpio0>; 926bd9cac1eSRicky CX Wu interrupts = <98 IRQ_TYPE_LEVEL_LOW>; 927bd9cac1eSRicky CX Wu gpio-line-names = "HSC1_ALERT1_R_N", "HSC2_ALERT1_R_N", 928bd9cac1eSRicky CX Wu "HSC3_ALERT1_R_N", "HSC4_ALERT1_R_N", 929bd9cac1eSRicky CX Wu "HSC5_ALERT1_R_N", "HSC6_ALERT1_R_N", 930bd9cac1eSRicky CX Wu "HSC7_ALERT1_R_N", "HSC8_ALERT1_R_N", 931bd9cac1eSRicky CX Wu "HSC1_ALERT2_R_N", "HSC2_ALERT2_R_N", 932bd9cac1eSRicky CX Wu "HSC3_ALERT2_R_N", "HSC4_ALERT2_R_N", 933bd9cac1eSRicky CX Wu "HSC5_ALERT2_R_N", "HSC6_ALERT2_R_N", 934bd9cac1eSRicky CX Wu "HSC7_ALERT2_R_N", "HSC8_ALERT2_R_N"; 9352b8d94f4SDelphine CC Chiu }; 9362b8d94f4SDelphine CC Chiu 9372b8d94f4SDelphine CC Chiu temperature-sensor@48 { 9382b8d94f4SDelphine CC Chiu compatible = "ti,tmp75"; 9392b8d94f4SDelphine CC Chiu reg = <0x48>; 9402b8d94f4SDelphine CC Chiu }; 9412b8d94f4SDelphine CC Chiu 9422b8d94f4SDelphine CC Chiu temperature-sensor@49 { 9432b8d94f4SDelphine CC Chiu compatible = "ti,tmp75"; 9442b8d94f4SDelphine CC Chiu reg = <0x49>; 9452b8d94f4SDelphine CC Chiu }; 9462b8d94f4SDelphine CC Chiu 9472b8d94f4SDelphine CC Chiu eeprom@54 { 94849d055f2SRicky CX Wu compatible = "atmel,24c128"; 9492b8d94f4SDelphine CC Chiu reg = <0x54>; 9502b8d94f4SDelphine CC Chiu }; 9512b8d94f4SDelphine CC Chiu}; 9522b8d94f4SDelphine CC Chiu 9532b8d94f4SDelphine CC Chiu&i2c12 { 954932df9afSRicky CX Wu #address-cells = <1>; 955932df9afSRicky CX Wu #size-cells = <0>; 9562b8d94f4SDelphine CC Chiu status = "okay"; 9572b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 9582b8d94f4SDelphine CC Chiu 959932df9afSRicky CX Wu i2c-mux@70 { 960932df9afSRicky CX Wu compatible = "nxp,pca9544"; 961932df9afSRicky CX Wu reg = <0x70>; 962932df9afSRicky CX Wu #address-cells = <1>; 963932df9afSRicky CX Wu #size-cells = <0>; 964932df9afSRicky CX Wu i2c-mux-idle-disconnect; 965932df9afSRicky CX Wu 966932df9afSRicky CX Wu imux34: i2c@0 { 967932df9afSRicky CX Wu reg = <0>; 968932df9afSRicky CX Wu #address-cells = <1>; 969932df9afSRicky CX Wu #size-cells = <0>; 970932df9afSRicky CX Wu 9712b8d94f4SDelphine CC Chiu temperature-sensor@48 { 9722b8d94f4SDelphine CC Chiu compatible = "ti,tmp75"; 9732b8d94f4SDelphine CC Chiu reg = <0x48>; 9742b8d94f4SDelphine CC Chiu }; 9752b8d94f4SDelphine CC Chiu 9762b8d94f4SDelphine CC Chiu eeprom@50 { 9772b8d94f4SDelphine CC Chiu compatible = "atmel,24c128"; 9782b8d94f4SDelphine CC Chiu reg = <0x50>; 9792b8d94f4SDelphine CC Chiu }; 9802b8d94f4SDelphine CC Chiu 981932df9afSRicky CX Wu eeprom@54 { 982932df9afSRicky CX Wu compatible = "atmel,24c64"; 983932df9afSRicky CX Wu reg = <0x54>; 984932df9afSRicky CX Wu }; 985932df9afSRicky CX Wu 9862b8d94f4SDelphine CC Chiu rtc@6f { 9872b8d94f4SDelphine CC Chiu compatible = "nuvoton,nct3018y"; 9882b8d94f4SDelphine CC Chiu reg = <0x6f>; 9892b8d94f4SDelphine CC Chiu }; 990932df9afSRicky CX Wu 991932df9afSRicky CX Wu gpio@20 { 992932df9afSRicky CX Wu compatible = "nxp,pca9506"; 993932df9afSRicky CX Wu reg = <0x20>; 994932df9afSRicky CX Wu gpio-controller; 995932df9afSRicky CX Wu #gpio-cells = <2>; 996932df9afSRicky CX Wu }; 997932df9afSRicky CX Wu 998932df9afSRicky CX Wu gpio@21 { 999932df9afSRicky CX Wu compatible = "nxp,pca9506"; 1000932df9afSRicky CX Wu reg = <0x21>; 1001932df9afSRicky CX Wu gpio-controller; 1002932df9afSRicky CX Wu #gpio-cells = <2>; 1003932df9afSRicky CX Wu }; 1004932df9afSRicky CX Wu 1005932df9afSRicky CX Wu gpio@22 { 1006932df9afSRicky CX Wu compatible = "nxp,pca9506"; 1007932df9afSRicky CX Wu reg = <0x22>; 1008932df9afSRicky CX Wu gpio-controller; 1009932df9afSRicky CX Wu #gpio-cells = <2>; 1010932df9afSRicky CX Wu }; 1011932df9afSRicky CX Wu 1012932df9afSRicky CX Wu gpio@23 { 1013932df9afSRicky CX Wu compatible = "nxp,pca9506"; 1014932df9afSRicky CX Wu reg = <0x23>; 1015932df9afSRicky CX Wu gpio-controller; 1016932df9afSRicky CX Wu #gpio-cells = <2>; 1017932df9afSRicky CX Wu }; 1018932df9afSRicky CX Wu }; 1019932df9afSRicky CX Wu 1020932df9afSRicky CX Wu imux35: i2c@1 { 1021932df9afSRicky CX Wu reg = <1>; 1022932df9afSRicky CX Wu #address-cells = <1>; 1023932df9afSRicky CX Wu #size-cells = <0>; 1024932df9afSRicky CX Wu }; 1025932df9afSRicky CX Wu }; 10262b8d94f4SDelphine CC Chiu}; 10272b8d94f4SDelphine CC Chiu 10282b8d94f4SDelphine CC Chiu&i2c13 { 10292b8d94f4SDelphine CC Chiu status = "okay"; 10303798cc53SDelphine CC Chiu bus-frequency = <100000>; 1031f6daa123SDelphine CC Chiu multi-master; 1032f6daa123SDelphine CC Chiu 1033f6daa123SDelphine CC Chiu ipmb@10 { 1034f6daa123SDelphine CC Chiu compatible = "ipmb-dev"; 1035f6daa123SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 1036f6daa123SDelphine CC Chiu i2c-protocol; 1037f6daa123SDelphine CC Chiu }; 10382b8d94f4SDelphine CC Chiu}; 10392b8d94f4SDelphine CC Chiu 10402b8d94f4SDelphine CC Chiu&i2c14 { 10419c4ce0cdSRicky CX Wu #address-cells = <1>; 10429c4ce0cdSRicky CX Wu #size-cells = <0>; 10432b8d94f4SDelphine CC Chiu status = "okay"; 10442b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 10452b8d94f4SDelphine CC Chiu adc@1d { 10462b8d94f4SDelphine CC Chiu compatible = "ti,adc128d818"; 10472b8d94f4SDelphine CC Chiu reg = <0x1d>; 10484b2e1630SRicky CX Wu ti,mode = /bits/ 8 <1>; 10492b8d94f4SDelphine CC Chiu }; 10502b8d94f4SDelphine CC Chiu 10514b2e1630SRicky CX Wu adc@36 { 10522b8d94f4SDelphine CC Chiu compatible = "ti,adc128d818"; 10534b2e1630SRicky CX Wu reg = <0x36>; 10544b2e1630SRicky CX Wu ti,mode = /bits/ 8 <1>; 10552b8d94f4SDelphine CC Chiu }; 10562b8d94f4SDelphine CC Chiu 10572b8d94f4SDelphine CC Chiu adc@37 { 10582b8d94f4SDelphine CC Chiu compatible = "ti,adc128d818"; 10592b8d94f4SDelphine CC Chiu reg = <0x37>; 10604b2e1630SRicky CX Wu ti,mode = /bits/ 8 <1>; 10612b8d94f4SDelphine CC Chiu }; 10622b8d94f4SDelphine CC Chiu 10632b8d94f4SDelphine CC Chiu power-sensor@40 { 10642b8d94f4SDelphine CC Chiu compatible = "ti,ina230"; 10652b8d94f4SDelphine CC Chiu reg = <0x40>; 10662b8d94f4SDelphine CC Chiu }; 10672b8d94f4SDelphine CC Chiu 10682b8d94f4SDelphine CC Chiu power-sensor@41 { 10692b8d94f4SDelphine CC Chiu compatible = "ti,ina230"; 10702b8d94f4SDelphine CC Chiu reg = <0x41>; 10712b8d94f4SDelphine CC Chiu }; 10722b8d94f4SDelphine CC Chiu 10732b8d94f4SDelphine CC Chiu power-sensor@42 { 10742b8d94f4SDelphine CC Chiu compatible = "ti,ina230"; 10752b8d94f4SDelphine CC Chiu reg = <0x42>; 10762b8d94f4SDelphine CC Chiu }; 10772b8d94f4SDelphine CC Chiu 10782b8d94f4SDelphine CC Chiu power-sensor@43 { 10792b8d94f4SDelphine CC Chiu compatible = "ti,ina230"; 10802b8d94f4SDelphine CC Chiu reg = <0x43>; 10812b8d94f4SDelphine CC Chiu }; 10822b8d94f4SDelphine CC Chiu 10832b8d94f4SDelphine CC Chiu power-sensor@44 { 10842b8d94f4SDelphine CC Chiu compatible = "ti,ina230"; 10852b8d94f4SDelphine CC Chiu reg = <0x44>; 10862b8d94f4SDelphine CC Chiu }; 10872b8d94f4SDelphine CC Chiu 10882b8d94f4SDelphine CC Chiu temperature-sensor@4e { 10892b8d94f4SDelphine CC Chiu compatible = "ti,tmp75"; 10902b8d94f4SDelphine CC Chiu reg = <0x4e>; 10912b8d94f4SDelphine CC Chiu }; 10922b8d94f4SDelphine CC Chiu 10932b8d94f4SDelphine CC Chiu temperature-sensor@4f { 10942b8d94f4SDelphine CC Chiu compatible = "ti,tmp75"; 10952b8d94f4SDelphine CC Chiu reg = <0x4f>; 10962b8d94f4SDelphine CC Chiu }; 10972b8d94f4SDelphine CC Chiu 10982b8d94f4SDelphine CC Chiu eeprom@51 { 10992b8d94f4SDelphine CC Chiu compatible = "atmel,24c128"; 11002b8d94f4SDelphine CC Chiu reg = <0x51>; 11012b8d94f4SDelphine CC Chiu }; 11022b8d94f4SDelphine CC Chiu 11032b8d94f4SDelphine CC Chiu i2c-mux@73 { 11042b8d94f4SDelphine CC Chiu compatible = "nxp,pca9544"; 11052b8d94f4SDelphine CC Chiu reg = <0x73>; 11062b8d94f4SDelphine CC Chiu #address-cells = <1>; 11072b8d94f4SDelphine CC Chiu #size-cells = <0>; 1108ca32ea32SRicky CX Wu i2c-mux-idle-disconnect; 11092b8d94f4SDelphine CC Chiu 1110ca32ea32SRicky CX Wu imux32: i2c@0 { 1111ca32ea32SRicky CX Wu reg = <0>; 1112ca32ea32SRicky CX Wu #address-cells = <1>; 1113ca32ea32SRicky CX Wu #size-cells = <0>; 11142b8d94f4SDelphine CC Chiu adc@35 { 11152b8d94f4SDelphine CC Chiu compatible = "maxim,max11617"; 11162b8d94f4SDelphine CC Chiu reg = <0x35>; 11172b8d94f4SDelphine CC Chiu }; 11182b8d94f4SDelphine CC Chiu }; 11192b8d94f4SDelphine CC Chiu 1120ca32ea32SRicky CX Wu imux33: i2c@1 { 1121ca32ea32SRicky CX Wu reg = <1>; 11222b8d94f4SDelphine CC Chiu #address-cells = <1>; 11232b8d94f4SDelphine CC Chiu #size-cells = <0>; 11242b8d94f4SDelphine CC Chiu adc@35 { 11252b8d94f4SDelphine CC Chiu compatible = "maxim,max11617"; 11262b8d94f4SDelphine CC Chiu reg = <0x35>; 11272b8d94f4SDelphine CC Chiu }; 11282b8d94f4SDelphine CC Chiu }; 11292b8d94f4SDelphine CC Chiu }; 11309c4ce0cdSRicky CX Wu 11319c4ce0cdSRicky CX Wu i2c-mux@74 { 11329c4ce0cdSRicky CX Wu compatible = "nxp,pca9546"; 11339c4ce0cdSRicky CX Wu reg = <0x74>; 11349c4ce0cdSRicky CX Wu #address-cells = <1>; 11359c4ce0cdSRicky CX Wu #size-cells = <0>; 11369c4ce0cdSRicky CX Wu i2c-mux-idle-disconnect; 11379c4ce0cdSRicky CX Wu 11389c4ce0cdSRicky CX Wu imux30: i2c@0 { 11399c4ce0cdSRicky CX Wu reg = <0>; 11409c4ce0cdSRicky CX Wu #address-cells = <1>; 11419c4ce0cdSRicky CX Wu #size-cells = <0>; 11429c4ce0cdSRicky CX Wu 11439c4ce0cdSRicky CX Wu adc@1f { 11449c4ce0cdSRicky CX Wu compatible = "ti,adc128d818"; 11459c4ce0cdSRicky CX Wu reg = <0x1f>; 1146622e9f72SRicky CX Wu ti,mode = /bits/ 8 <1>; 11479c4ce0cdSRicky CX Wu }; 11489c4ce0cdSRicky CX Wu 11499c4ce0cdSRicky CX Wu pwm@20{ 11509c4ce0cdSRicky CX Wu compatible = "maxim,max31790"; 11519c4ce0cdSRicky CX Wu reg = <0x20>; 11529c4ce0cdSRicky CX Wu }; 11539c4ce0cdSRicky CX Wu 11549c4ce0cdSRicky CX Wu gpio@22{ 11559c4ce0cdSRicky CX Wu compatible = "ti,tca6424"; 11569c4ce0cdSRicky CX Wu reg = <0x22>; 11579c4ce0cdSRicky CX Wu gpio-controller; 11589c4ce0cdSRicky CX Wu #gpio-cells = <2>; 11599c4ce0cdSRicky CX Wu }; 11609c4ce0cdSRicky CX Wu 11610eaf75b6SRicky CX Wu pwm@2f{ 11629c4ce0cdSRicky CX Wu compatible = "maxim,max31790"; 11630eaf75b6SRicky CX Wu reg = <0x2f>; 11649c4ce0cdSRicky CX Wu }; 11659c4ce0cdSRicky CX Wu 11669c4ce0cdSRicky CX Wu adc@33 { 11679c4ce0cdSRicky CX Wu compatible = "maxim,max11615"; 11689c4ce0cdSRicky CX Wu reg = <0x33>; 11699c4ce0cdSRicky CX Wu }; 11709c4ce0cdSRicky CX Wu 11719c4ce0cdSRicky CX Wu eeprom@52 { 11729c4ce0cdSRicky CX Wu compatible = "atmel,24c128"; 11739c4ce0cdSRicky CX Wu reg = <0x52>; 11749c4ce0cdSRicky CX Wu }; 11759c4ce0cdSRicky CX Wu 11769c4ce0cdSRicky CX Wu gpio@61 { 11779c4ce0cdSRicky CX Wu compatible = "nxp,pca9552"; 11789c4ce0cdSRicky CX Wu reg = <0x61>; 11799c4ce0cdSRicky CX Wu #address-cells = <1>; 11809c4ce0cdSRicky CX Wu #size-cells = <0>; 11819c4ce0cdSRicky CX Wu gpio-controller; 11829c4ce0cdSRicky CX Wu #gpio-cells = <2>; 11839c4ce0cdSRicky CX Wu }; 11849c4ce0cdSRicky CX Wu }; 11859c4ce0cdSRicky CX Wu 11869c4ce0cdSRicky CX Wu imux31: i2c@1 { 11879c4ce0cdSRicky CX Wu reg = <1>; 11889c4ce0cdSRicky CX Wu #address-cells = <1>; 11899c4ce0cdSRicky CX Wu #size-cells = <0>; 11909c4ce0cdSRicky CX Wu 11919c4ce0cdSRicky CX Wu adc@1f { 11929c4ce0cdSRicky CX Wu compatible = "ti,adc128d818"; 11939c4ce0cdSRicky CX Wu reg = <0x1f>; 1194622e9f72SRicky CX Wu ti,mode = /bits/ 8 <1>; 11959c4ce0cdSRicky CX Wu }; 11969c4ce0cdSRicky CX Wu 11979c4ce0cdSRicky CX Wu pwm@20{ 11989c4ce0cdSRicky CX Wu compatible = "maxim,max31790"; 11999c4ce0cdSRicky CX Wu reg = <0x20>; 12009c4ce0cdSRicky CX Wu }; 12019c4ce0cdSRicky CX Wu 12029c4ce0cdSRicky CX Wu gpio@22{ 12039c4ce0cdSRicky CX Wu compatible = "ti,tca6424"; 12049c4ce0cdSRicky CX Wu reg = <0x22>; 12059c4ce0cdSRicky CX Wu gpio-controller; 12069c4ce0cdSRicky CX Wu #gpio-cells = <2>; 12079c4ce0cdSRicky CX Wu }; 12089c4ce0cdSRicky CX Wu 12090eaf75b6SRicky CX Wu pwm@2f{ 12109c4ce0cdSRicky CX Wu compatible = "maxim,max31790"; 12110eaf75b6SRicky CX Wu reg = <0x2f>; 12129c4ce0cdSRicky CX Wu }; 12139c4ce0cdSRicky CX Wu 12149c4ce0cdSRicky CX Wu adc@33 { 12159c4ce0cdSRicky CX Wu compatible = "maxim,max11615"; 12169c4ce0cdSRicky CX Wu reg = <0x33>; 12179c4ce0cdSRicky CX Wu }; 12189c4ce0cdSRicky CX Wu 12199c4ce0cdSRicky CX Wu eeprom@52 { 12209c4ce0cdSRicky CX Wu compatible = "atmel,24c128"; 12219c4ce0cdSRicky CX Wu reg = <0x52>; 12229c4ce0cdSRicky CX Wu }; 12239c4ce0cdSRicky CX Wu 12249c4ce0cdSRicky CX Wu gpio@61 { 12259c4ce0cdSRicky CX Wu compatible = "nxp,pca9552"; 12269c4ce0cdSRicky CX Wu reg = <0x61>; 12279c4ce0cdSRicky CX Wu #address-cells = <1>; 12289c4ce0cdSRicky CX Wu #size-cells = <0>; 12299c4ce0cdSRicky CX Wu gpio-controller; 12309c4ce0cdSRicky CX Wu #gpio-cells = <2>; 12319c4ce0cdSRicky CX Wu }; 12329c4ce0cdSRicky CX Wu }; 12339c4ce0cdSRicky CX Wu }; 12342b8d94f4SDelphine CC Chiu}; 12352b8d94f4SDelphine CC Chiu 12362b8d94f4SDelphine CC Chiu&i2c15 { 123740542a3dSRicky CX Wu #address-cells = <1>; 123840542a3dSRicky CX Wu #size-cells = <0>; 12392b8d94f4SDelphine CC Chiu status = "okay"; 12402b8d94f4SDelphine CC Chiu multi-master; 12412b8d94f4SDelphine CC Chiu bus-frequency = <400000>; 12422b8d94f4SDelphine CC Chiu 12432b8d94f4SDelphine CC Chiu mctp@10 { 12442b8d94f4SDelphine CC Chiu compatible = "mctp-i2c-controller"; 12452b8d94f4SDelphine CC Chiu reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; 12462b8d94f4SDelphine CC Chiu }; 12472b8d94f4SDelphine CC Chiu 12482b8d94f4SDelphine CC Chiu i2c-mux@72 { 12492b8d94f4SDelphine CC Chiu compatible = "nxp,pca9544"; 12502b8d94f4SDelphine CC Chiu reg = <0x72>; 125140542a3dSRicky CX Wu #address-cells = <1>; 125240542a3dSRicky CX Wu #size-cells = <0>; 125340542a3dSRicky CX Wu 125440542a3dSRicky CX Wu imux24: i2c@0 { 125540542a3dSRicky CX Wu reg = <0>; 125640542a3dSRicky CX Wu #address-cells = <1>; 125740542a3dSRicky CX Wu #size-cells = <0>; 125840542a3dSRicky CX Wu mctp-controller; 125940542a3dSRicky CX Wu temperature-sensor@1f { 126040542a3dSRicky CX Wu compatible = "ti,tmp421"; 126140542a3dSRicky CX Wu reg = <0x1f>; 126240542a3dSRicky CX Wu }; 126340542a3dSRicky CX Wu 126440542a3dSRicky CX Wu eeprom@50 { 126540542a3dSRicky CX Wu compatible = "atmel,24c64"; 126640542a3dSRicky CX Wu reg = <0x50>; 126740542a3dSRicky CX Wu }; 126840542a3dSRicky CX Wu }; 126940542a3dSRicky CX Wu 127040542a3dSRicky CX Wu imux25: i2c@1 { 127140542a3dSRicky CX Wu reg = <1>; 127240542a3dSRicky CX Wu #address-cells = <1>; 127340542a3dSRicky CX Wu #size-cells = <0>; 127440542a3dSRicky CX Wu mctp-controller; 127540542a3dSRicky CX Wu temperature-sensor@1f { 127640542a3dSRicky CX Wu compatible = "ti,tmp421"; 127740542a3dSRicky CX Wu reg = <0x1f>; 127840542a3dSRicky CX Wu }; 127940542a3dSRicky CX Wu 128040542a3dSRicky CX Wu eeprom@50 { 128140542a3dSRicky CX Wu compatible = "atmel,24c64"; 128240542a3dSRicky CX Wu reg = <0x50>; 128340542a3dSRicky CX Wu }; 128440542a3dSRicky CX Wu }; 128540542a3dSRicky CX Wu 128640542a3dSRicky CX Wu imux26: i2c@2 { 128740542a3dSRicky CX Wu reg = <2>; 128840542a3dSRicky CX Wu #address-cells = <1>; 128940542a3dSRicky CX Wu #size-cells = <0>; 129040542a3dSRicky CX Wu mctp-controller; 129140542a3dSRicky CX Wu temperature-sensor@1f { 129240542a3dSRicky CX Wu compatible = "ti,tmp421"; 129340542a3dSRicky CX Wu reg = <0x1f>; 129440542a3dSRicky CX Wu }; 129540542a3dSRicky CX Wu 129640542a3dSRicky CX Wu eeprom@50 { 129740542a3dSRicky CX Wu compatible = "atmel,24c64"; 129840542a3dSRicky CX Wu reg = <0x50>; 129940542a3dSRicky CX Wu }; 130040542a3dSRicky CX Wu }; 130140542a3dSRicky CX Wu 130240542a3dSRicky CX Wu imux27: i2c@3 { 130340542a3dSRicky CX Wu reg = <3>; 130440542a3dSRicky CX Wu #address-cells = <1>; 130540542a3dSRicky CX Wu #size-cells = <0>; 130640542a3dSRicky CX Wu mctp-controller; 130740542a3dSRicky CX Wu temperature-sensor@1f { 130840542a3dSRicky CX Wu compatible = "ti,tmp421"; 130940542a3dSRicky CX Wu reg = <0x1f>; 131040542a3dSRicky CX Wu }; 131140542a3dSRicky CX Wu 131240542a3dSRicky CX Wu eeprom@50 { 131340542a3dSRicky CX Wu compatible = "atmel,24c64"; 131440542a3dSRicky CX Wu reg = <0x50>; 131540542a3dSRicky CX Wu }; 131640542a3dSRicky CX Wu }; 13172b8d94f4SDelphine CC Chiu }; 13182b8d94f4SDelphine CC Chiu}; 13192b8d94f4SDelphine CC Chiu 13202b8d94f4SDelphine CC Chiu&adc0 { 13212b8d94f4SDelphine CC Chiu status = "okay"; 13222b8d94f4SDelphine CC Chiu pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default 13232b8d94f4SDelphine CC Chiu &pinctrl_adc2_default &pinctrl_adc3_default 13242b8d94f4SDelphine CC Chiu &pinctrl_adc4_default &pinctrl_adc5_default 13252b8d94f4SDelphine CC Chiu &pinctrl_adc6_default &pinctrl_adc7_default>; 13262b8d94f4SDelphine CC Chiu}; 13272b8d94f4SDelphine CC Chiu 13282b8d94f4SDelphine CC Chiu&adc1 { 13292b8d94f4SDelphine CC Chiu status = "okay"; 1330d943e59cSRicky CX Wu pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default 1331d943e59cSRicky CX Wu &pinctrl_adc15_default>; 13322b8d94f4SDelphine CC Chiu}; 13332b8d94f4SDelphine CC Chiu 13342b8d94f4SDelphine CC Chiu&ehci0 { 13352b8d94f4SDelphine CC Chiu status = "okay"; 13362b8d94f4SDelphine CC Chiu}; 13372b8d94f4SDelphine CC Chiu 13382b8d94f4SDelphine CC Chiu&ehci1 { 13392b8d94f4SDelphine CC Chiu status = "okay"; 13402b8d94f4SDelphine CC Chiu}; 13412b8d94f4SDelphine CC Chiu 13422b8d94f4SDelphine CC Chiu&uhci { 13432b8d94f4SDelphine CC Chiu status = "okay"; 13442b8d94f4SDelphine CC Chiu}; 1345