1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare PCIe interface 8 9maintainers: 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12 13description: | 14 Synopsys DesignWare PCIe host controller 15 16# Please create a separate DT-schema for your DWC PCIe Root Port controller 17# and make sure it's assigned with the vendor-specific compatible string. 18select: 19 properties: 20 compatible: 21 const: snps,dw-pcie 22 required: 23 - compatible 24 25allOf: 26 - $ref: /schemas/pci/pci-bus.yaml# 27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 28 29properties: 30 reg: 31 description: | 32 It should contain Data Bus Interface (dbi) and config registers for all 33 versions. 34 For designware core version >= 4.80, it may contain ATU address space. 35 minItems: 2 36 maxItems: 5 37 38 reg-names: 39 minItems: 2 40 maxItems: 5 41 items: 42 enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl, 43 parf, cfg, link, ulreg, smu, mpu, apb, phy ] 44 45 interrupts: true 46 47 interrupt-names: true 48 49 clocks: true 50 51additionalProperties: true 52 53required: 54 - compatible 55 - reg 56 - reg-names 57 58examples: 59 - | 60 pcie@dfc00000 { 61 compatible = "snps,dw-pcie"; 62 device_type = "pci"; 63 reg = <0xdfc00000 0x0001000>, /* IP registers */ 64 <0xd0000000 0x0002000>; /* Configuration space */ 65 reg-names = "dbi", "config"; 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, 69 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; 70 bus-range = <0x0 0xff>; 71 72 interrupts = <25>, <24>; 73 #interrupt-cells = <1>; 74 75 reset-gpios = <&port0 0 1>; 76 77 phys = <&pcie_phy>; 78 phy-names = "pcie"; 79 80 num-lanes = <1>; 81 max-link-speed = <3>; 82 }; 83