1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare PCIe interface 8 9maintainers: 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12 13description: | 14 Synopsys DesignWare PCIe host controller 15 16# Please create a separate DT-schema for your DWC PCIe Root Port controller 17# and make sure it's assigned with the vendor-specific compatible string. 18select: 19 properties: 20 compatible: 21 const: snps,dw-pcie 22 required: 23 - compatible 24 25allOf: 26 - $ref: /schemas/pci/pci-bus.yaml# 27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 28 29properties: 30 reg: 31 description: | 32 It should contain Data Bus Interface (dbi) and config registers for all 33 versions. 34 For designware core version >= 4.80, it may contain ATU address space. 35 minItems: 2 36 maxItems: 5 37 38 reg-names: 39 minItems: 2 40 maxItems: 5 41 items: 42 enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl, 43 parf, cfg, link, ulreg, smu, mpu, apb, phy ] 44 45 interrupts: 46 description: 47 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt 48 signal is supposed to be specified for the host controller. 49 minItems: 1 50 maxItems: 26 51 52 interrupt-names: 53 minItems: 1 54 maxItems: 26 55 items: 56 oneOf: 57 - description: 58 Controller request to read or write virtual product data 59 from/to the VPD capability registers. 60 const: vpd 61 - description: 62 Link Equalization Request flag is set in the Link Status 2 63 register (applicable if the corresponding IRQ is enabled in 64 the Link Control 3 register). 65 const: l_eq 66 - description: 67 Indicates that the eDMA Tx/Rx transfer is complete or that an 68 error has occurred on the corresponding channel. eDMA can have 69 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up 70 to 16 IRQ signals all together. Write eDMA channels shall go 71 first in the ordered row as per default edma_int[*] bus setup. 72 pattern: '^dma([0-9]|1[0-5])?$' 73 - description: 74 PCIe protocol correctable error or a Data Path protection 75 correctable error is detected by the automotive/safety 76 feature. 77 const: sft_ce 78 - description: 79 Indicates that the internal safety mechanism has detected an 80 uncorrectable error. 81 const: sft_ue 82 - description: 83 Application-specific IRQ raised depending on the vendor-specific 84 events basis. 85 const: app 86 - description: 87 DSP AXI MSI Interrupt detected. It gets de-asserted when there is 88 no more MSI interrupt pending. The interrupt is relevant to the 89 iMSI-RX - Integrated MSI Receiver (AXI bridge). 90 const: msi 91 - description: 92 Legacy A/B/C/D interrupt signal. Basically it's triggered by 93 receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message 94 from the downstream device. 95 pattern: "^int(a|b|c|d)$" 96 - description: 97 Error condition detected and a flag is set in the Root Error Status 98 register of the AER capability. It's asserted when the RC 99 internally generated an error or an error message is received by 100 the RC. 101 const: aer 102 - description: 103 PME message is received by the port. That means having the PME 104 status bit set in the Root Status register (the event is 105 supposed to be unmasked in the Root Control register). 106 const: pme 107 - description: 108 Hot-plug event is detected. That is a bit has been set in the 109 Slot Status register and the corresponding event is enabled in 110 the Slot Control register. 111 const: hp 112 - description: 113 Link Autonomous Bandwidth Status flag has been set in the Link 114 Status register (the event is supposed to be unmasked in the 115 Link Control register). 116 const: bw_au 117 - description: 118 Bandwidth Management Status flag has been set in the Link 119 Status register (the event is supposed to be unmasked in the 120 Link Control register). 121 const: bw_mg 122 - description: 123 Vendor-specific IRQ names. Consider using the generic names above 124 for new bindings. 125 oneOf: 126 - description: See native "app" IRQ for details 127 enum: [ intr ] 128 allOf: 129 - contains: 130 const: msi 131 132 clocks: true 133 134additionalProperties: true 135 136required: 137 - compatible 138 - reg 139 - reg-names 140 141examples: 142 - | 143 pcie@dfc00000 { 144 compatible = "snps,dw-pcie"; 145 device_type = "pci"; 146 reg = <0xdfc00000 0x0001000>, /* IP registers */ 147 <0xd0000000 0x0002000>; /* Configuration space */ 148 reg-names = "dbi", "config"; 149 #address-cells = <3>; 150 #size-cells = <2>; 151 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, 152 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; 153 bus-range = <0x0 0xff>; 154 155 interrupts = <25>, <24>; 156 interrupt-names = "msi", "hp"; 157 #interrupt-cells = <1>; 158 159 reset-gpios = <&port0 0 1>; 160 161 phys = <&pcie_phy>; 162 phy-names = "pcie"; 163 164 num-lanes = <1>; 165 max-link-speed = <3>; 166 }; 167