xref: /openbmc/linux/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml (revision 78e29356d6d2fb455c8318f3201c8884e75f9e09) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: HiSilicon Kirin SoCs PCIe host DT description
8
9maintainers:
10  - Xiaowei Song <songxiaowei@hisilicon.com>
11  - Binghui Wang <wangbinghui@hisilicon.com>
12
13description: |
14  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15  It shares common functions with the PCIe DesignWare core driver and
16  inherits common properties defined in
17  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
18
19allOf:
20  - $ref: /schemas/pci/snps,dw-pcie.yaml#
21
22properties:
23  compatible:
24    contains:
25      enum:
26        - hisilicon,kirin960-pcie
27
28  reg:
29    description: |
30      Should contain dbi, apb, config registers location and length.
31      For HiKey960, it should also contain phy.
32    minItems: 3
33    maxItems: 4
34
35  reg-names:
36    minItems: 3
37    maxItems: 4
38
39required:
40  - compatible
41  - reg
42  - reg-names
43
44unevaluatedProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/interrupt-controller/arm-gic.h>
49    #include <dt-bindings/clock/hi3660-clock.h>
50
51    soc {
52      #address-cells = <2>;
53      #size-cells = <2>;
54
55      pcie@f4000000 {
56        compatible = "hisilicon,kirin960-pcie";
57        reg = <0x0 0xf4000000 0x0 0x1000>,
58              <0x0 0xff3fe000 0x0 0x1000>,
59              <0x0 0xf3f20000 0x0 0x40000>,
60              <0x0 0xf5000000 0x0 0x2000>;
61        reg-names = "dbi", "apb", "phy", "config";
62        bus-range = <0x0  0xff>;
63        #address-cells = <3>;
64        #size-cells = <2>;
65        device_type = "pci";
66        ranges = <0x02000000 0x0 0x00000000
67                  0x0 0xf6000000
68                  0x0 0x02000000>;
69        num-lanes = <1>;
70        #interrupt-cells = <1>;
71        interrupts = <0 283 4>;
72        interrupt-names = "msi";
73        interrupt-map-mask = <0xf800 0 0 7>;
74        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
75                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
76                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
77                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
78        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
79                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
80                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
81                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
82                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
83        clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
84                      "pcie_apb_sys", "pcie_aclk";
85      };
86    };
87