| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 320 unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST; in mv_ddr_rtt_wr_get() local
323 rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1]; in mv_ddr_rtt_wr_get()
325 if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) { in mv_ddr_rtt_wr_get()
327 rtt_wr = PARAM_UNDEFINED; in mv_ddr_rtt_wr_get()
330 return rtt_wr; in mv_ddr_rtt_wr_get()
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| H A D | ddr_topology_def.h | 73 enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM]; member
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| /openbmc/u-boot/board/udoo/ |
| H A D | udoo_spl.c | 188 .rtt_wr = 2,
217 mem_qdl.rtt_wr = 1; in spl_dram_init()
224 mem_qdl.rtt_wr = 2; in spl_dram_init()
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| /openbmc/u-boot/board/engicam/common/ |
| H A D | spl.c | 241 .rtt_wr = 2,
273 .rtt_wr = 1,
290 .rtt_wr = 1,
337 .rtt_wr = 2,
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| /openbmc/u-boot/board/liebherr/mccmon6/ |
| H A D | spl.c | 182 .rtt_wr = 0,
223 .rtt_wr = 0,
240 .rtt_wr = 0,
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ctrl_regs.c | 984 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2() local
992 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
994 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
1001 | ((rtt_wr & 0x3) << 9) in set_ddr_sdram_mode_2()
1025 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
1027 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; in set_ddr_sdram_mode_2()
1030 esdmode2 |= (rtt_wr & 0x3) << 9; in set_ddr_sdram_mode_2()
1071 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2() local
1078 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
1080 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
[all …]
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| /openbmc/u-boot/board/wandboard/ |
| H A D | spl.c | 231 .rtt_wr = 0,
274 .rtt_wr = 0,
293 .rtt_wr = 0,
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| /openbmc/u-boot/board/compulab/cm_fx6/ |
| H A D | spl.c | 101 .rtt_wr = 0,
168 .rtt_wr = 0,
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| /openbmc/u-boot/board/bachmann/ot1200/ |
| H A D | ot1200_spl.c | 77 .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
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| /openbmc/u-boot/board/ccv/xpress/ |
| H A D | spl.c | 53 .rtt_wr = 2,
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| /openbmc/u-boot/board/barco/platinum/ |
| H A D | spl_picon.c | 125 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ in spl_dram_init()
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| H A D | spl_titanium.c | 128 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ in spl_dram_init()
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| /openbmc/u-boot/board/sks-kinkel/sksimx6/ |
| H A D | sksimx6.c | 329 .rtt_wr = 1,
358 mem_qdl.rtt_wr = 1; in spl_dram_init()
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| /openbmc/u-boot/board/phytec/pcl063/ |
| H A D | spl.c | 57 .rtt_wr = 1,
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| /openbmc/u-boot/board/bticino/mamoj/ |
| H A D | spl.c | 120 .rtt_wr = 1,
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 121 .rtt_wr = 2,
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| H A D | opos6ul.c | 186 .rtt_wr = 2,
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| /openbmc/u-boot/board/technexion/pico-imx6ul/ |
| H A D | spl.c | 67 .rtt_wr = 0,
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| /openbmc/u-boot/board/dhelectronics/dh_imx6/ |
| H A D | dh_imx6_spl.c | 244 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
263 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
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| /openbmc/u-boot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 634 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
670 .rtt_wr = 2,
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| /openbmc/u-boot/board/liebherr/display5/ |
| H A D | spl.c | 173 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ in spl_dram_init()
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| /openbmc/u-boot/board/k+p/kp_imx6q_tpc/ |
| H A D | kp_imx6q_tpc_spl.c | 236 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ in spl_dram_init()
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| /openbmc/u-boot/board/freescale/mx6slevk/ |
| H A D | mx6slevk.c | 409 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ in spl_dram_init()
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| /openbmc/u-boot/board/phytec/pcm058/ |
| H A D | pcm058.c | 499 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ in spl_dram_init()
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| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | spl.c | 224 .rtt_wr = CONFIG_RTT_WR,
|