Searched refs:SPRN_L1CSR0 (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_e500.S | 32 mfspr r0, SPRN_L1CSR0
38 mtspr SPRN_L1CSR0, r0 /* Disable */
42 mtspr SPRN_L1CSR0, r0 /* Invalidate */
44 1: mfspr r0, SPRN_L1CSR0
51 mtspr SPRN_L1CSR0, r0 /* Enable */
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 122 mtspr SPRN_L1CSR0,r2
124 mfspr r3,SPRN_L1CSR0
130 mtspr SPRN_L1CSR0,r3
133 mfspr r3,SPRN_L1CSR0
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| H A D | start.S | 791 mtspr SPRN_L1CSR0,r2
793 mfspr r3,SPRN_L1CSR0
799 mtspr SPRN_L1CSR0,r3
802 mfspr r3,SPRN_L1CSR0
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| /openbmc/linux/arch/powerpc/kvm/ |
| H A D | e500_emulate.c | 248 case SPRN_L1CSR0: in kvmppc_core_emulate_mtspr_e500()
378 case SPRN_L1CSR0: in kvmppc_core_emulate_mfspr_e500()
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 485 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ macro
733 #define L1CSR0 SPRN_L1CSR0
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 173 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ macro
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