Home
last modified time | relevance | path

Searched refs:ARM_CP_CONST (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcortex-regs.c40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
H A Ddebug_helper.c951 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
955 .type = ARM_CP_CONST, .resetvalue = 0 },
958 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
974 .type = ARM_CP_CONST, .resetvalue = 0 },
984 .type = ARM_CP_CONST, .resetvalue = 0 },
988 .type = ARM_CP_CONST, .resetvalue = 0 },
993 .type = ARM_CP_CONST, .resetvalue = 0 },
1003 .type = ARM_CP_CONST, .resetvalue = 0 },
1084 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO_GDB,
1087 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BI
[all...]
H A Dhelper.c67 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg()
87 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg()
112 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid()
725 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
734 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
887 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2274 .access = PL1_R, .type = ARM_CP_CONST,
2287 .type = ARM_CP_CONST, .resetvalue = 0 },
2293 .type = ARM_CP_CONST, .resetvalue = 0 },
3676 .type = ARM_CP_CONST, in do_ats_write()
[all...]
H A Dcpregs.h50 ARM_CP_CONST = 1 << 4, enumerator
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
487 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
490 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
493 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
496 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
515 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
[all …]
H A Dcpu32.c338 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
340 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
407 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
476 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
578 .access = PL1_RW, .type = ARM_CP_CONST },
580 .access = PL1_RW, .type = ARM_CP_CONST },
617 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
[all …]
H A Dtranslate.c3113 if (ri->type & ARM_CP_CONST) { in do_coproc_insn()
3133 if (ri->type & ARM_CP_CONST) { in do_coproc_insn()
3155 if (ri->type & ARM_CP_CONST) { in do_coproc_insn()
H A Dtranslate-a64.c2547 if (ri->type & ARM_CP_CONST) { in handle_sys()
2558 if (ri->type & ARM_CP_CONST) { in handle_sys()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2569 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2597 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2613 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
/openbmc/qemu/target/arm/hvf/
H A Dhvf.c1263 if (ri->type & ARM_CP_CONST) { in hvf_sysreg_read_cp()