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/openbmc/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
32 access the SPI NOR flash on platforms embedding this Altera
41 used to access the SPI NOR flash on boards using the Aspeed
63 to access SPI NOR flash and other SPI peripherals. This driver
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
80 access the SPI NOR flash on platforms embedding this Broadcom
88 access the SPI NOR flash on platforms embedding these Broadcom
94 Enable the Broadcom set-top box SPI driver. This driver can
99 bool "Cadence QSPI driver"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
H A Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
14 as NOR flash.
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
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H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
[all …]
H A Dfsl,spi-fsl-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
13 - $ref: spi-controller.yaml#
18 - enum:
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
[all …]
H A Dnvidia,tegra210-quad.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 - $ref: spi-controller.yaml#
19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
[all …]
H A Dst,stm32-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Patrice Chotard <patrice.chotard@foss.st.com>
14 - $ref: spi-controller.yaml#
18 const: st,stm32f469-qspi
22 - description: registers
[all …]
H A Datmel,quadspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Quad Serial Peripheral Interface (QSPI)
10 - Tudor Ambarus <tudor.ambarus@linaro.org>
13 - $ref: spi-controller.yaml#
18 - atmel,sama5d2-qspi
19 - microchip,sam9x60-qspi
20 - microchip,sama7g5-qspi
21 - microchip,sama7g5-ospi
[all …]
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME2 --------
3 The LS2080A Reference Design (RDB) is a high-performance computing,
7 The LS2081A Reference Design (RDB) is a high-performance computing,
12 --------------------------------------
13 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
17 -----------------------
18 - SERDES Connections, 16 lanes supporting:
19 - PCI Express - 3.0
20 - SATA 3.0
21 - XFI
[all …]
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME2 --------
3 The LS1088A Reference Design (RDB) is a high-performance computing,
9 --------------------------------------
10 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
13 -------------------------------------------
15 For QSPI Boot
36 Alternately you can use this command to switch from QSPI to SD
41 -------------------------
42 - SERDES Connections, 16 lanes supporting:
43 - PCI Express - 3.0
[all …]
/openbmc/u-boot/board/freescale/ls1012ardb/
H A DREADME2 --------
3 QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
[all …]
/openbmc/u-boot/include/configs/
H A Ddra7xx_evm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
81 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
82 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
83 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
84 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
85 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
86 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
87 * 0x9E0000 - 0x2000000 : USERLAND
144 /* Parallel NOR Support */
146 /* NOR: device related configs */
[all …]
H A Dzynq-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * (C) Copyright 2013 - 2018 Xilinx, Inc.
44 /* QSPI */
46 /* NOR */
140 # define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
152 # define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na)
169 "qspi "
184 "nor "
223 "env import -t ${loadbootenv_addr} $filesize\0" \
224 "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
[all …]
/openbmc/u-boot/doc/
H A DREADME.ti-secure22 Booting of U-Boot SPL
25 When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process
36 ${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
38 This is called as part of the SPL/u-boot build process. As the secure
49 create-boot-image.sh \
55 SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
56 X-LOADER - Generates an image for non-XIP flash
57 MLO - Generates an image for SD/MMC/eMMC media
58 2ND - Generates an image for USB, UART and Ethernet
59 XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
[all …]
H A DREADME.zynq1 # SPDX-License-Identifier: GPL-2.0+
3 # Xilinx ZYNQ U-Boot
9 This document describes the information about Xilinx Zynq U-Boot -
14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
18 * zc702 (single qspi, gem0, mmc) [1]
19 * zc706 (dual parallel qspi, gem0, mmc) [2]
20 * zed (single qspi, gem0, mmc) [3]
21 * microzed (single qspi, gem0, mmc) [4]
23 - zc770-xm010 (single qspi, gem0, mmc)
24 - zc770-xm011 (8 or 16 bit nand)
[all …]
/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
118 to SPI NOR chips, and support for the SPI flash memory
120 only supports SPI NOR.
145 supports spi-mem interface.
206 based platforms. This driver works for both SPI master for SPI NOR
224 this code to manage the per-word or per-transfer accesses to the
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.qspi1 QSPI Boot source support Overview
2 -------------------
14 Booting from QSPI
15 -------------------
16 Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
17 The difference between QSPI boot RCW image and NOR boot image is the PBI
19 to the address for u-boot in QSPI flash.
21 RCW image should be written to the beginning of QSPI flash device.
22 Example of using u-boot command
31 To get the QSPI image, build u-boot with QSPI config, for example,
[all …]
/openbmc/u-boot/board/freescale/ls1012aqds/
H A DREADME2 --------
3 QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
6 optimized to support the high-bandwidth DDR3L memory and
7 a full complement of high-speed SerDes ports.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt1 Cadence QSPI controller device tree bindings
2 --------------------------------------------
5 - compatible : should be "cdns,qspi-nor"
6 - reg : 1.Physical base address and size of SPI registers map.
7 2. Physical base address & size of NOR Flash.
8 - clocks : Clock phandles (see clock bindings for details).
9 - cdns,fifo-depth : Size of the data FIFO in words.
10 - cdns,fifo-width : Bus width of the data FIFO in bytes.
11 - cdns,trigger-address : 32-bit indirect AHB trigger address.
12 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
[all …]
H A Dspi-stm32-qspi.txt1 STM32 QSPI controller device tree bindings
2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
7 2. Physical base address & size of mapped NOR Flash.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 &qspi {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-max-frequency = <100000000>;
19 m25p,fast-read;
20 cdns,page-size = <256>;
21 cdns,block-size = <16>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dls1021a-iot.dtsi1 // SPDX-License-Identifier: GPL-2.0+
15 enet2-rgmii-phy = &rgmii_phy1;
16 enet0-sgmii-phy = &sgmii_phy2;
17 enet1-sgmii-phy = &sgmii_phy0;
18 spi0 = &qspi;
23 &qspi {
24 bus-num = <0>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "spi-flash";
[all …]
/openbmc/u-boot/drivers/mtd/spi/
H A Dspi-nor-tiny.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
40 if (op->data.dir == SPI_MEM_DATA_IN) in spi_nor_read_write_reg()
41 op->data.buf.in = buf; in spi_nor_read_write_reg()
43 op->data.buf.out = buf; in spi_nor_read_write_reg()
44 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) in spi_nor_read_reg() argument
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7742-iwg21m.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 regulator-boot-on;
35 clock-frequency = <20000000>;
39 /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
[all …]
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME2 --------
3 The LS2080A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
[all …]

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