18097cba8SVikas ManochaCadence QSPI controller device tree bindings 28097cba8SVikas Manocha-------------------------------------------- 38097cba8SVikas Manocha 48097cba8SVikas ManochaRequired properties: 5*2a3a9993SSimon Goldschmidt- compatible : should be "cdns,qspi-nor" 68097cba8SVikas Manocha- reg : 1.Physical base address and size of SPI registers map. 78097cba8SVikas Manocha 2. Physical base address & size of NOR Flash. 88097cba8SVikas Manocha- clocks : Clock phandles (see clock bindings for details). 9c58f3006SJason Rush- cdns,fifo-depth : Size of the data FIFO in words. 10c58f3006SJason Rush- cdns,fifo-width : Bus width of the data FIFO in bytes. 11c58f3006SJason Rush- cdns,trigger-address : 32-bit indirect AHB trigger address. 12c58f3006SJason Rush- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. 138097cba8SVikas Manocha- status : enable in requried dts. 148097cba8SVikas Manocha 158097cba8SVikas Manochaconnected flash properties 168097cba8SVikas Manocha-------------------------- 178097cba8SVikas Manocha 188097cba8SVikas Manocha- spi-max-frequency : Max supported spi frequency. 198097cba8SVikas Manocha- page-size : Flash page size. 208097cba8SVikas Manocha- block-size : Flash memory block size. 21c58f3006SJason Rush- cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for 228097cba8SVikas Manocha the length that the master mode chip select outputs 238097cba8SVikas Manocha are de-asserted between transactions. 24c58f3006SJason Rush- cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one 258097cba8SVikas Manocha chip select being de-activated and the activation of 268097cba8SVikas Manocha another. 27c58f3006SJason Rush- cdns,tchsh-ns : Delay in master reference clocks between last bit of 288097cba8SVikas Manocha current transaction and de-asserting the device chip 298097cba8SVikas Manocha select (n_ss_out). 30c58f3006SJason Rush- cdns,tslch-ns : Delay in master reference clocks between setting 318097cba8SVikas Manocha n_ss_out low and first bit transfer 32