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/openbmc/linux/arch/powerpc/kernel/
H A Ddt_cpu_ftrs.c70 u64 lpcr; member
80 mtspr(SPRN_LPCR, system_registers.lpcr); in __restore_cpu_cpufeatures()
128 * LPCR does not get cleared, to match behaviour with secondaries in cpufeatures_setup_cpu()
130 * could clear LPCR too. in cpufeatures_setup_cpu()
211 u64 lpcr; in feat_enable_hv() local
221 lpcr = mfspr(SPRN_LPCR); in feat_enable_hv()
222 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ in feat_enable_hv()
223 mtspr(SPRN_LPCR, lpcr); in feat_enable_hv()
245 u64 lpcr; in feat_enable_idle_nap() local
248 lpcr = mfspr(SPRN_LPCR); in feat_enable_idle_nap()
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H A Dcpu_setup_power.c29 static void init_LPCR_ISA300(u64 lpcr, u64 lpes) in init_LPCR_ISA300() argument
32 lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES; in init_LPCR_ISA300()
33 lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2; in init_LPCR_ISA300()
34 lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD; in init_LPCR_ISA300()
35 lpcr &= ~LPCR_HDICE; /* clear HDICE */ in init_LPCR_ISA300()
36 lpcr |= (4ull << LPCR_VC_SH); in init_LPCR_ISA300()
37 mtspr(SPRN_LPCR, lpcr); in init_LPCR_ISA300()
42 * Setup a sane LPCR:
43 * Called with initial LPCR and desired LPES 2-bit value
54 static void init_LPCR_ISA206(u64 lpcr, u64 lpes) in init_LPCR_ISA206() argument
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/openbmc/qemu/target/ppc/
H A Dexcp_helper.c240 * are delivered in this way. AIL requires the LPCR to be set to enable this
249 * radix mode (LPCR[HR]).
251 * POWER8, POWER9 with LPCR[HR]=0
252 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
260 * POWER9 with LPCR[HR]=1
261 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
274 * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
281 * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
344 /* HV interrupts depend on LPCR[HAIL] */ in ppc_excp_apply_ail()
1681 target_ulong lpcr) in p7_interrupt_powersave() argument
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H A Dmmu-hash64.c722 /* If ISL is set in LPCR we need to clamp the page size to 4K */ in ppc_hash64_htab_lookup()
931 * ISA v3.0 removes the LPCR[VRMASD] field and puts the VRMA base in get_vrma_llp()
946 uint64_t lpcr = env->spr[SPR_LPCR]; in get_vrma_llp() local
947 target_ulong vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; in get_vrma_llp()
999 * Note on LPCR usage: 970 uses HID4, but our special variant of in ppc_hash64_xlate()
1001 * Similarly we filter unimplemented bits when storing into LPCR in ppc_hash64_xlate()
1003 * LPCR "as-is". in ppc_hash64_xlate()
H A Dmmu-book3s-v3.h74 * The LPCR:HR bit is a shortcut that avoids having to
/openbmc/qemu/hw/misc/
H A Dimx7_snvs.c35 VMSTATE_UINT64(lpcr, IMX7SNVSState),
60 ret = s->lpcr; in imx7_snvs_read()
73 s->lpcr = 0; in imx7_snvs_reset()
97 s->lpcr = v; in imx7_snvs_write()
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv.c480 pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.16lx\n", in kvmppc_dump_regs()
481 vcpu->arch.vcore->lpcr, vcpu->kvm->arch.sdr1, in kvmppc_dump_regs()
2100 * Enforce limits on guest LPCR values based on hardware availability,
2104 unsigned long kvmppc_filter_lpcr_hv(struct kvm *kvm, unsigned long lpcr) in kvmppc_filter_lpcr_hv() argument
2108 lpcr &= ~LPCR_TC; in kvmppc_filter_lpcr_hv()
2112 lpcr &= ~LPCR_AIL; in kvmppc_filter_lpcr_hv()
2113 if ((lpcr & LPCR_AIL) != LPCR_AIL_3) in kvmppc_filter_lpcr_hv()
2114 lpcr &= ~LPCR_AIL; /* LPCR[AIL]=1/2 is disallowed */ in kvmppc_filter_lpcr_hv()
2122 lpcr &= ~LPCR_AIL; in kvmppc_filter_lpcr_hv()
2129 lpcr &= ~LPCR_LD; in kvmppc_filter_lpcr_hv()
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H A Dbook3s_hv_builtin.c535 * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and in inject_interrupt()
543 (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && in inject_interrupt()
569 unsigned long lpcr; in kvmppc_guest_entry_inject_int() local
573 /* Insert EXTERNAL bit into LPCR at the MER bit position */ in kvmppc_guest_entry_inject_int()
575 lpcr = mfspr(SPRN_LPCR); in kvmppc_guest_entry_inject_int()
576 lpcr |= ext << LPCR_MER_SH; in kvmppc_guest_entry_inject_int()
577 mtspr(SPRN_LPCR, lpcr); in kvmppc_guest_entry_inject_int()
585 if (!(lpcr & LPCR_LD)) in kvmppc_guest_entry_inject_int()
H A Dbook3s_hv_p9_entry.c301 static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_radix() argument
318 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_radix()
326 static void switch_mmu_to_guest_hpt(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_hpt() argument
343 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_hpt()
356 u64 lpcr = kvm->arch.host_lpcr; in switch_mmu_to_host() local
368 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_host()
532 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr, u64 *tb) in kvmhv_vcpu_entry_p9() argument
698 switch_mmu_to_guest_radix(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
700 switch_mmu_to_guest_hpt(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
706 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, in kvmhv_vcpu_entry_p9()
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H A Dbook3s_hv_nested.c72 hr->lpcr = swab64(hr->lpcr); in byteswap_hv_regs()
261 const struct hv_guest_state *l1_hv, u64 *lpcr) in load_l2_hv_regs() argument
269 * Don't let L1 change LPCR bits for the L2 except these: in load_l2_hv_regs()
277 *lpcr = kvmppc_filter_lpcr_hv(vcpu->kvm, in load_l2_hv_regs()
278 (vc->lpcr & ~mask) | (*lpcr & mask)); in load_l2_hv_regs()
303 u64 hdec_exp, lpcr; in kvmhv_enter_nested_guest() local
378 lpcr = l2_hv.lpcr; in kvmhv_enter_nested_guest()
379 load_l2_hv_regs(vcpu, &l2_hv, &saved_l1_hv, &lpcr); in kvmhv_enter_nested_guest()
384 r = kvmhv_run_single_vcpu(vcpu, hdec_exp, lpcr); in kvmhv_enter_nested_guest()
H A Dbook3s_hv_interrupts.S63 * we need to set LPCR[HDICE] before writing HDEC.
/openbmc/qemu/hw/ppc/
H A Dspapr_cpu_core.c35 target_ulong lpcr; in spapr_reset_vcpu() local
51 lpcr = env->spr[SPR_LPCR]; in spapr_reset_vcpu()
53 /* Set emulated LPCR to not send interrupts to hypervisor. Note that in spapr_reset_vcpu()
54 * under KVM, the actual HW LPCR will be set differently by KVM itself, in spapr_reset_vcpu()
62 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); in spapr_reset_vcpu()
63 lpcr |= LPCR_LPES0 | LPCR_LPES1; in spapr_reset_vcpu()
66 ppc_store_lpcr(cpu, lpcr); in spapr_reset_vcpu()
H A Dspapr_rtas.c135 target_ulong lpcr; in rtas_start_cpu() local
167 lpcr = env->spr[SPR_LPCR]; in rtas_start_cpu()
170 lpcr = (lpcr & ~LPCR_ILE) | (caller_lpcr & LPCR_ILE); in rtas_start_cpu()
173 lpcr = (lpcr & ~LPCR_AIL) | (caller_lpcr & LPCR_AIL); in rtas_start_cpu()
181 lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; in rtas_start_cpu()
183 lpcr &= ~(LPCR_UPRT | LPCR_GTSE | LPCR_HR); in rtas_start_cpu()
187 ppc_store_lpcr(newcpu, lpcr); in rtas_start_cpu()
H A Dspapr_nested.c152 save->lpcr = env->spr[SPR_LPCR]; in nested_save_state()
251 env->spr[SPR_LPCR] = load->lpcr; in nested_load_state()
337 target_ulong lpcr, lpcr_mask; in h_enter_nested() local
406 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); in h_enter_nested()
407 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; in h_enter_nested()
408 lpcr &= ~LPCR_LPES0; in h_enter_nested()
409 l2_state.lpcr = lpcr & pcc->lpcr_mask; in h_enter_nested()
504 hvstate->lpcr = l2_state.lpcr; in spapr_exit_nested_hv()
882 GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR),
1743 target_ulong lpcr, lpcr_mask, hdec; in nested_papr_load_l2() local
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H A Dspapr_caps.c575 target_ulong lpcr = env->spr[SPR_LPCR]; in cap_large_decr_cpu_apply() local
586 lpcr |= LPCR_LD; in cap_large_decr_cpu_apply()
588 lpcr &= ~LPCR_LD; in cap_large_decr_cpu_apply()
590 ppc_store_lpcr(cpu, lpcr); in cap_large_decr_cpu_apply()
/openbmc/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c70 /* Values for LPCR Register */
144 u32 lpcr, lvcr, lhcr; in imx_lcdc_update_hw_registers() local
176 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
177 lpcr &= ~IMX21LCDC_LPCR_BPIX; in imx_lcdc_update_hw_registers()
178 lpcr |= FIELD_PREP(IMX21LCDC_LPCR_BPIX, imx_lcdc_get_format(fb->format->format)); in imx_lcdc_update_hw_registers()
179 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsmp.c205 * offline, so clear LPCR:PECE1. We keep PECE2 (and in pnv_cpu_offline_self()
209 * the SLW engine sets LPCR with decrementer bit cleared, else in pnv_cpu_offline_self()
284 * Re-enable decrementer interrupts in LPCR. in pnv_cpu_offline_self()
287 * for non-hotplug cases. So program the LPCR via stop api as in pnv_cpu_offline_self()
H A Didle.c70 * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across in pnv_save_sprs_for_deep_states()
299 u64 lpcr; member
349 sprs.lpcr = mfspr(SPRN_LPCR); in power7_idle_insn()
483 mtspr(SPRN_LPCR, sprs.lpcr); in power7_idle_insn()
587 u64 lpcr; member
664 sprs.lpcr = mfspr(SPRN_LPCR); in power9_idle_stop()
780 mtspr(SPRN_LPCR, sprs.lpcr); in power9_idle_stop()
1047 * Program the LPCR via stop-api only if the deepest stop state in pnv_program_cpu_hotplug_lpcr()
1117 * 1 - Exit from power-save mode controlled by LPCR's PECE bits
/openbmc/linux/drivers/rtc/
H A Drtc-snvs.c137 u32 lpcr; in snvs_rtc_enable() local
143 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); in snvs_rtc_enable()
146 if (lpcr & SNVS_LPCR_SRTC_ENV) in snvs_rtc_enable()
149 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) in snvs_rtc_enable()
/openbmc/linux/arch/powerpc/mm/book3s64/
H A Dradix_pgtable.c532 unsigned long lpcr; in radix__early_init_mmu() local
578 lpcr = mfspr(SPRN_LPCR); in radix__early_init_mmu()
579 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); in radix__early_init_mmu()
594 unsigned long lpcr; in radix__early_init_mmu_secondary() local
599 lpcr = mfspr(SPRN_LPCR); in radix__early_init_mmu_secondary()
600 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); in radix__early_init_mmu_secondary()
616 unsigned long lpcr; in radix__mmu_cleanup_all() local
619 lpcr = mfspr(SPRN_LPCR); in radix__mmu_cleanup_all()
620 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); in radix__mmu_cleanup_all()
/openbmc/linux/arch/powerpc/include/asm/
H A Dkvm_book3s.h89 ulong lpcr; member
262 unsigned long lpcr);
263 extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,
311 u64 time_limit, unsigned long lpcr);
H A Dpnv-ocxl.h79 uint64_t lpcr, void __iomem **arva);
/openbmc/qemu/include/hw/misc/
H A Dimx7_snvs.h38 uint64_t lpcr; member
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl,sec-v4.0-mon.yaml125 SNVS_LP LPCR register.
/openbmc/qemu/include/hw/ppc/
H A Dspapr_nested.h361 uint64_t lpcr; member
427 uint64_t lpcr; member

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