/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument 42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument 43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument 45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument 46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument [all …]
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H A D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument 70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument 72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument 73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument 75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument 76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument 78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument 79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument 81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument 82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument [all …]
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H A D | rv515d.h | 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument 211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument 213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument 214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument 216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument 217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument 219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument 220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument 222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument 223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument [all …]
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H A D | rs690d.h | 34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument 36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument 37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument 39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument 40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument 43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument 44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument 47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument 48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument 51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument [all …]
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H A D | r420d.h | 32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument 33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument 35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument 36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument 39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument 40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument 43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument [all …]
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H A D | r300d.h | 70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument 71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument 73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument 74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument 77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument 78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument 80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument 81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument 84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument 85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument [all …]
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H A D | r600d.h | 60 #define BACKEND_DISABLE(x) ((x) << 16) argument 63 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) argument 64 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) argument 83 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument 84 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument 86 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument 87 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument 97 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) argument 98 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) argument 100 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) argument [all …]
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H A D | r520d.h | 33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument 34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument 37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument 38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument 44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument 45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument 47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument 48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument [all …]
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H A D | rs400d.h | 33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument 34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument 36 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument 37 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument 40 #define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument 41 #define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument 43 #define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument 44 #define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument 47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument 48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument [all …]
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H A D | evergreend.h | 53 #define HOST_SMC_MSG(x) ((x) << 0) argument 56 #define HOST_SMC_RESP(x) ((x) << 8) argument 59 #define SMC_HOST_MSG(x) ((x) << 16) argument 62 #define SMC_HOST_RESP(x) ((x) << 24) argument 67 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument 70 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument 78 #define SPLL_REF_DIV(x) ((x) << 4) argument 80 #define SPLL_PDIV_A(x) ((x) << 20) argument 83 #define SCLK_MUX_SEL(x) ((x) << 0) argument 87 #define SPLL_FB_DIV(x) ((x) << 0) argument [all …]
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H A D | rv770d.h | 47 # define UPLL_REF_DIV(x) ((x) << 16) argument 52 # define UPLL_SW_HILEN(x) ((x) << 0) argument 53 # define UPLL_SW_LOLEN(x) ((x) << 4) argument 54 # define UPLL_SW_HILEN2(x) ((x) << 8) argument 55 # define UPLL_SW_LOLEN2(x) ((x) << 12) argument 57 # define VCLK_SRC_SEL(x) ((x) << 20) argument 59 # define DCLK_SRC_SEL(x) ((x) << 25) argument 62 # define UPLL_FB_DIV(x) ((x) << 0) argument 74 #define HOST_SMC_MSG(x) ((x) << 0) argument 77 #define HOST_SMC_RESP(x) ((x) << 8) argument [all …]
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H A D | rv250d.h | 32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument 33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument 35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument 36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument 38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument 39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument 41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument 42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument 44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument 45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument [all …]
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/openbmc/u-boot/include/andestech/ |
H A D | andes_pcu.h | 79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument 80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument 85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument 86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument 91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument 92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument 93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument 98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument 99 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument 100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument [all …]
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/openbmc/u-boot/include/synopsys/ |
H A D | dwcddr21mctl.h | 47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument 48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument 49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument 50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument 51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument 52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument 53 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument 54 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument 55 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument 56 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument [all …]
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/openbmc/linux/drivers/media/platform/verisilicon/ |
H A D | rockchip_vpu2_regs.h | 14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument 15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument 17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument 18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument 20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument 21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument 23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument 24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument 25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument 27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument [all …]
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H A D | hantro_g1_regs.h | 28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument 37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument 41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument 45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument 47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument 70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0) argument 74 #define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) argument 75 #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) argument 76 #define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) argument 77 #define G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) argument [all …]
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/openbmc/linux/lib/crypto/ |
H A D | chacha.c | 16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument 24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute() 25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute() 26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute() 27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute() 29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute() 30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute() 31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute() 32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute() 34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute() [all …]
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/openbmc/u-boot/board/samsung/odroid/ |
H A D | setup.h | 11 #define SDIV(x) ((x) & 0x7) argument 12 #define PDIV(x) (((x) & 0x3f) << 8) argument 13 #define MDIV(x) (((x) & 0x3ff) << 16) argument 14 #define FSEL(x) (((x) & 0x1) << 27) argument 16 #define PLL_ENABLE(x) (((x) & 0x1) << 31) argument 19 #define MUX_APLL_SEL(x) ((x) & 0x1) argument 20 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) argument 21 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) argument 22 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) argument 27 #define APLL_SEL(x) ((x) & 0x7) argument [all …]
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/openbmc/linux/drivers/phy/microchip/ |
H A D | sparx5_serdes_regs.h | 35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument 36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x) 37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument 38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x) 41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument 42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x) 43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument 44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x) 47 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument 48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/ |
H A D | regs.h | 36 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument 40 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument 44 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument 48 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument 52 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument 56 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument 61 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument 62 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument 65 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument 69 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | vop_rk3288.h | 122 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument 123 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument 124 #define V_DMA_STOP(x) (((x) & 1) << 21) argument 125 #define V_MMU_EN(x) (((x) & 1) << 20) argument 126 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) argument 127 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) argument 128 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) argument 129 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) argument 130 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) argument 131 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) argument [all …]
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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_main_regs.h | 65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument 66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument 68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument 72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument 74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument 82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/ |
H A D | regs.h | 5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument 9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument 13 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument 17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument 21 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument 26 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument 30 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument 33 #define V_FLMODE(x) ((x) << S_FLMODE) argument 38 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument 41 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument [all …]
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/openbmc/u-boot/arch/m68k/include/asm/ |
H A D | m5329.h | 17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument 18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument 19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument 20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument 21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument 22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument 39 #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) argument 40 #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) argument 41 #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) argument 47 #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) argument [all …]
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/openbmc/linux/drivers/net/ethernet/microchip/lan966x/ |
H A D | lan966x_regs.h | 38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ argument 39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument 41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument 48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument 50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ argument 54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) [all …]
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