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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_timer.S31 wsr a2, ccount
65 wsr a2, intenable
67 wsr a2, intclear
70 wsr a2, ccompare1
73 wsr a2, ccompare2
76 wsr a2, ccompare0
80 wsr a2, ccount
90 wsr a2, intenable
92 wsr a2, intclear
95 wsr a2, ccompare1
[all …]
H A Dtest_interrupt.S47 wsr a2, intenable
49 wsr a2, ccompare0
52 wsr a2, ccompare1
55 wsr a2, ccompare2
59 wsr a2, intclear
97 wsr a2, intset
103 wsr a2, intclear
119 wsr a2, intset
126 wsr a2, intenable
138 wsr a2, intset
[all …]
H A Dtest_break.S64 wsr a2, ibreaka0
66 wsr a2, ibreakenable
71 wsr a2, ibreaka0
73 wsr a2, ibreakenable
78 wsr a2, ibreaka0
80 wsr a2, ibreakenable
102 wsr a2, ibreaka0
105 wsr a3, ibreakenable
125 wsr a2, ps
136 wsr a2, ibreaka0
[all …]
H A Dtest_loop.S50 wsr a3, lcount
51 wsr a4, lbeg
52 wsr a5, lend
68 wsr a4, ps
75 wsr a4, ps
84 wsr a3, lcount
85 wsr a4, lbeg
86 wsr a5, lend
97 wsr a3, lbeg
109 wsr a3, lcount
[all …]
H A Dtest_windowed.S11 wsr a2, windowstart
14 wsr a2, windowbase
17 wsr a2, windowstart
27 wsr a2, windowstart
40 wsr a2, epc1
104 wsr a2, epc1
220 wsr a2, windowstart
223 wsr a2, windowstart
248 wsr a2, windowstart
291 wsr a2, ps
[all …]
H A Dtest_s32c1i.S10 wsr a2, atomctl
14 wsr a3, scompare1
31 wsr a2, atomctl
35 wsr a3, scompare1
H A Dcrt.S13 wsr a2, windowstart
15 wsr a2, windowbase
19 wsr a2, ps
/openbmc/linux/arch/xtensa/kernel/
H A Dhead.S58 wsr a2, excsave1
73 wsr a1, windowstart
74 wsr a0, windowbase
79 wsr a1, ps
97 wsr a2, excsave1
119 wsr a2, vecbase
126 wsr a0, ibreakenable
128 wsr a0, icount
130 wsr a0, icountlevel
134 wsr a0, SREG_DBREAKC + _index
[all …]
H A Dentry.S138 wsr a2, depc # terminate user stack trace with 0
236 wsr a3, windowstart # set corresponding WINDOWSTART bit
237 wsr a2, windowbase # and WINDOWSTART
579 wsr abi_tmp0, scompare1
581 wsr abi_saved1, ps /* disable interrupts */
593 wsr a1, depc # use DEPC as temp storage
594 wsr a3, windowstart # restore WINDOWSTART
743 wsr a2, epc1
744 wsr a3, sar
750 wsr a2, lbeg
[all …]
H A Dvectors.S75 wsr a2, depc # save a2
102 wsr a2, depc # save a2
261 wsr a2, depc # save stack pointer temporarily
264 wsr a0, windowbase
313 wsr a0, excsave1
407 wsr a0, depc # replace the saved a0
416 wsr a0, depc # replace the saved a0
456 wsr a2, depc
539 wsr a2, depc
642 wsr a0, excsave2
[all …]
H A Dmxhead.S43 wsr a1, windowstart
44 wsr a0, windowbase
49 wsr a1, ps
/openbmc/u-boot/arch/xtensa/cpu/
H A Dstart.S91 wsr a0, PTEVADDR
99 wsr a0, DBREAKC + _index
108 wsr a3, windowstart
109 wsr a0, windowbase
121 wsr a3, VECBASE
127 wsr a0, LCOUNT
137 wsr a2, PS
205 wsr a2, PS
306 wsr a0, windowstart
341 wsr a2, EXCSAVE1
[all …]
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dtie-asm.h158 wsr.ACCLO \at1 // MAC16 option
160 wsr.ACCHI \at1 // MAC16 option
170 wsr.BR \at1 // boolean option
172 wsr.SCOMPARE1 \at1 // conditional store option
174 wsr.M0 \at1 // MAC16 option
176 wsr.M1 \at1 // MAC16 option
178 wsr.M2 \at1 // MAC16 option
180 wsr.M3 \at1 // MAC16 option
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dtie-asm.h136 wsr.ACCLO \at1 // MAC16 option
138 wsr.ACCHI \at1 // MAC16 option
148 wsr.SCOMPARE1 \at1 // conditional store option
150 wsr.M0 \at1 // MAC16 option
152 wsr.M1 \at1 // MAC16 option
154 wsr.M2 \at1 // MAC16 option
156 wsr.M3 \at1 // MAC16 option
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dtie-asm.h84 wsr \at1, ACCLO // MAC16 accumulator
85 wsr \at2, ACCHI
92 wsr \at1, M0 // MAC16 registers
93 wsr \at2, M1
96 wsr \at1, M2
97 wsr \at2, M3
103 wsr \at1, SCOMPARE1 // conditional store option
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h115 wsr.ACCLO \at1 // MAC16 option
117 wsr.ACCHI \at1 // MAC16 option
127 wsr.SCOMPARE1 \at1 // conditional store option
129 wsr.M0 \at1 // MAC16 option
131 wsr.M1 \at1 // MAC16 option
133 wsr.M2 \at1 // MAC16 option
135 wsr.M3 \at1 // MAC16 option
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h82 wsr \at1, ACCLO // MAC16 accumulator
83 wsr \at2, ACCHI
90 wsr \at1, M0 // MAC16 registers
91 wsr \at2, M1
94 wsr \at1, M2
95 wsr \at2, M3
101 wsr \at1, SCOMPARE1 // conditional store option
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie-asm.h136 wsr \at1, ACCLO // MAC16 option
138 wsr \at1, ACCHI // MAC16 option
148 wsr \at1, M0 // MAC16 option
150 wsr \at1, M1 // MAC16 option
152 wsr \at1, M2 // MAC16 option
154 wsr \at1, M3 // MAC16 option
156 wsr \at1, SCOMPARE1 // conditional store option
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dtie-asm.h157 wsr \at1, ACCLO // MAC16 option
159 wsr \at1, ACCHI // MAC16 option
169 wsr \at1, M0 // MAC16 option
171 wsr \at1, M1 // MAC16 option
173 wsr \at1, M2 // MAC16 option
175 wsr \at1, M3 // MAC16 option
177 wsr \at1, SCOMPARE1 // conditional store option
/openbmc/u-boot/drivers/watchdog/
H A Dimx_watchdog.c22 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
23 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
57 writew(0x5555, &wdog->wsr); in reset_cpu()
58 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu.c293 out_be16(&wdt->wsr, 0x5555); in watchdog_reset()
294 out_be16(&wdt->wsr, 0xaaaa); in watchdog_reset()
302 out_be16(&wdt->wsr, 0x5555); in watchdog_disable()
303 out_be16(&wdt->wsr, 0xaaaa); in watchdog_disable()
324 out_be16(&wdt->wsr, 0x5555); in watchdog_init()
325 out_be16(&wdt->wsr, 0xaaaa); in watchdog_init()
/openbmc/linux/arch/xtensa/boot/boot-elf/
H A Dbootstrap.S47 wsr a0, windowbase
50 wsr a0, windowstart
54 wsr a0, ps
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie-asm.h158 wsr.ACCLO \at1 // MAC16 option
160 wsr.ACCHI \at1 // MAC16 option
170 wsr.BR \at1 // boolean option
172 wsr.SCOMPARE1 \at1 // conditional store option
174 wsr.M0 \at1 // MAC16 option
176 wsr.M1 \at1 // MAC16 option
178 wsr.M2 \at1 // MAC16 option
180 wsr.M3 \at1 // MAC16 option
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dreset.c32 writew(0x5555, &regs->wsr); in reset_cpu()
33 writew(0xAAAA, &regs->wsr); in reset_cpu()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/
H A Dreset.c32 writew(WSR_UNLOCK1, &regs->wsr); in reset_cpu()
33 writew(WSR_UNLOCK2, &regs->wsr); in reset_cpu()

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