1*367b8112SChris Zankel /* 2*367b8112SChris Zankel * This header file contains assembly-language definitions (assembly 3*367b8112SChris Zankel * macros, etc.) for this specific Xtensa processor's TIE extensions 4*367b8112SChris Zankel * and options. It is customized to this Xtensa processor configuration. 5*367b8112SChris Zankel * 6*367b8112SChris Zankel * This file is subject to the terms and conditions of the GNU General Public 7*367b8112SChris Zankel * License. See the file "COPYING" in the main directory of this archive 8*367b8112SChris Zankel * for more details. 9*367b8112SChris Zankel * 10*367b8112SChris Zankel * Copyright (C) 1999-2007 Tensilica Inc. 11*367b8112SChris Zankel */ 12*367b8112SChris Zankel 13*367b8112SChris Zankel #ifndef _XTENSA_CORE_TIE_ASM_H 14*367b8112SChris Zankel #define _XTENSA_CORE_TIE_ASM_H 15*367b8112SChris Zankel 16*367b8112SChris Zankel /* Selection parameter values for save-area save/restore macros: */ 17*367b8112SChris Zankel /* Option vs. TIE: */ 18*367b8112SChris Zankel #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 19*367b8112SChris Zankel #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 20*367b8112SChris Zankel /* Whether used automatically by compiler: */ 21*367b8112SChris Zankel #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 22*367b8112SChris Zankel #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 23*367b8112SChris Zankel /* ABI handling across function calls: */ 24*367b8112SChris Zankel #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25*367b8112SChris Zankel #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26*367b8112SChris Zankel #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27*367b8112SChris Zankel /* Misc */ 28*367b8112SChris Zankel #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 29*367b8112SChris Zankel 30*367b8112SChris Zankel 31*367b8112SChris Zankel 32*367b8112SChris Zankel /* Macro to save all non-coprocessor (extra) custom TIE and optional state 33*367b8112SChris Zankel * (not including zero-overhead loop registers). 34*367b8112SChris Zankel * Save area ptr (clobbered): ptr (1 byte aligned) 35*367b8112SChris Zankel * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 36*367b8112SChris Zankel */ 37*367b8112SChris Zankel .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 38*367b8112SChris Zankel xchal_sa_start \continue, \ofs 39*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 40*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-8, 4, 4 41*367b8112SChris Zankel rsr \at1, ACCLO // MAC16 accumulator 42*367b8112SChris Zankel rsr \at2, ACCHI 43*367b8112SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 44*367b8112SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 4 45*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 46*367b8112SChris Zankel .endif 47*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 48*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-16, 4, 4 49*367b8112SChris Zankel rsr \at1, M0 // MAC16 registers 50*367b8112SChris Zankel rsr \at2, M1 51*367b8112SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 52*367b8112SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 4 53*367b8112SChris Zankel rsr \at1, M2 54*367b8112SChris Zankel rsr \at2, M3 55*367b8112SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 8 56*367b8112SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 12 57*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 58*367b8112SChris Zankel .endif 59*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 60*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 61*367b8112SChris Zankel rsr \at1, SCOMPARE1 // conditional store option 62*367b8112SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 63*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 64*367b8112SChris Zankel .endif 65*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 66*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 67*367b8112SChris Zankel rur \at1, THREADPTR // threadptr option 68*367b8112SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 69*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 70*367b8112SChris Zankel .endif 71*367b8112SChris Zankel .endm // xchal_ncp_store 72*367b8112SChris Zankel 73*367b8112SChris Zankel /* Macro to save all non-coprocessor (extra) custom TIE and optional state 74*367b8112SChris Zankel * (not including zero-overhead loop registers). 75*367b8112SChris Zankel * Save area ptr (clobbered): ptr (1 byte aligned) 76*367b8112SChris Zankel * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 77*367b8112SChris Zankel */ 78*367b8112SChris Zankel .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 79*367b8112SChris Zankel xchal_sa_start \continue, \ofs 80*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 81*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-8, 4, 4 82*367b8112SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 83*367b8112SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 4 84*367b8112SChris Zankel wsr \at1, ACCLO // MAC16 accumulator 85*367b8112SChris Zankel wsr \at2, ACCHI 86*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 87*367b8112SChris Zankel .endif 88*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 89*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-16, 4, 4 90*367b8112SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 91*367b8112SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 4 92*367b8112SChris Zankel wsr \at1, M0 // MAC16 registers 93*367b8112SChris Zankel wsr \at2, M1 94*367b8112SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 8 95*367b8112SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 12 96*367b8112SChris Zankel wsr \at1, M2 97*367b8112SChris Zankel wsr \at2, M3 98*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 99*367b8112SChris Zankel .endif 100*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 101*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 102*367b8112SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 103*367b8112SChris Zankel wsr \at1, SCOMPARE1 // conditional store option 104*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 105*367b8112SChris Zankel .endif 106*367b8112SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 107*367b8112SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 108*367b8112SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 109*367b8112SChris Zankel wur \at1, THREADPTR // threadptr option 110*367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 111*367b8112SChris Zankel .endif 112*367b8112SChris Zankel .endm // xchal_ncp_load 113*367b8112SChris Zankel 114*367b8112SChris Zankel 115*367b8112SChris Zankel 116*367b8112SChris Zankel #define XCHAL_NCP_NUM_ATMPS 2 117*367b8112SChris Zankel 118*367b8112SChris Zankel 119*367b8112SChris Zankel #define XCHAL_SA_NUM_ATMPS 2 120*367b8112SChris Zankel 121*367b8112SChris Zankel #endif /*_XTENSA_CORE_TIE_ASM_H*/ 122*367b8112SChris Zankel 123