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Searched refs:wr32 (Results 1 – 25 of 102) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_tsn.c85 wr32(IGC_GTXOFFSET, txoffset); in igc_tsn_adjust_txtime_offset()
94 wr32(IGC_RETX_CTL, retxctl); in igc_tsn_restore_retx_default()
114 wr32(IGC_GTXOFFSET, 0); in igc_tsn_disable_offload()
115 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); in igc_tsn_disable_offload()
116 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT); in igc_tsn_disable_offload()
125 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_disable_offload()
128 wr32(IGC_TXQCTL(i), 0); in igc_tsn_disable_offload()
129 wr32(IGC_STQT(i), 0); in igc_tsn_disable_offload()
130 wr32(IGC_ENDQT(i), NSEC_PER_SEC); in igc_tsn_disable_offload()
133 wr32(IGC_QBVCYCLET_S, 0); in igc_tsn_disable_offload()
[all …]
H A Digc_base.c32 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
34 wr32(IGC_RCTL, 0); in igc_reset_hw_base()
35 wr32(IGC_TCTL, IGC_TCTL_PSP); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); in igc_reset_hw_base()
55 wr32(IGC_IMC, 0xffffffff); in igc_reset_hw_base()
119 wr32(IGC_CTRL, ctrl); in igc_setup_copper_link_base()
344 wr32(IGC_RFCTL, rfctl); in igc_rx_fifo_flush_base()
352 wr32(IGC_RXDCTL(i), in igc_rx_fifo_flush_base()
372 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); in igc_rx_fifo_flush_base()
375 wr32(IGC_RLPML, 0); in igc_rx_fifo_flush_base()
[all …]
H A Digc_ptp.c42 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
43 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
67 wr32(IGC_TIMINCA, inca); in igc_ptp_adjfine_i225()
204 wr32(IGC_TSSDP, tssdp); in igc_pin_perout()
205 wr32(IGC_CTRL, ctrl); in igc_pin_perout()
206 wr32(IGC_CTRL_EXT, ctrl_ext); in igc_pin_perout()
240 wr32(IGC_TSSDP, tssdp); in igc_pin_extts()
241 wr32(IGC_CTRL, ctrl); in igc_pin_extts()
242 wr32(IGC_CTRL_EXT, ctrl_ext); in igc_pin_extts()
296 wr32(IGC_TSAUXC, tsauxc); in igc_ptp_feature_enable_i225()
[all …]
H A Digc_diag.c46 wr32(reg, test_pattern[pat] & write); in reg_pattern_test()
53 wr32(reg, before); in reg_pattern_test()
56 wr32(reg, before); in reg_pattern_test()
68 wr32(reg, write & mask); in reg_set_and_check()
75 wr32(reg, before); in reg_set_and_check()
78 wr32(reg, before); in reg_set_and_check()
97 wr32(IGC_STATUS, toggle); in igc_reg_test()
107 wr32(IGC_STATUS, before); in igc_reg_test()
H A Digc_mac.c29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
103 wr32(IGC_FCRTL, fcrtl); in igc_set_fc_watermarks()
104 wr32(IGC_FCRTH, fcrth); in igc_set_fc_watermarks()
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE); in igc_setup_link()
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igc_setup_link()
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igc_setup_link()
158 wr32(IGC_FCTTV, hw->fc.pause_time); in igc_setup_link()
223 wr32(IGC_CTRL, ctrl); in igc_force_mac_fc()
341 wr32(IGC_RAL(index), rar_low); in igc_rar_set()
343 wr32(IGC_RAH(index), rar_high); in igc_rar_set()
[all …]
H A Digc_i225.c83 wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_i225()
141 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_acquire_swfw_sync_i225()
172 wr32(IGC_SW_FW_SYNC, swfw_sync); in igc_release_swfw_sync_i225()
249 wr32(IGC_SRWR, eewr); in igc_write_nvm_srwr()
384 wr32(IGC_EECD, flup); in igc_update_flash_i225()
545 wr32(IGC_IPCNFG, ipcnfg); in igc_set_eee_i225()
546 wr32(IGC_EEER, eeer); in igc_set_eee_i225()
578 wr32(IGC_LTRC, ltrc); in igc_set_ltr_i225()
629 wr32(IGC_LTRMINV, ltrv); in igc_set_ltr_i225()
636 wr32(IGC_LTRMAXV, ltrv); in igc_set_ltr_i225()
/openbmc/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c21 wr32(wx, WX_PX_IMS(0), mask); in wx_intr_disable()
26 wr32(wx, WX_PX_IMS(1), mask); in wx_intr_disable()
36 wr32(wx, WX_PX_IMC(0), mask); in wx_intr_enable()
40 wr32(wx, WX_PX_IMC(1), mask); in wx_intr_enable()
53 wr32(wx, WX_PX_MISC_IEN, 0); in wx_irq_disable()
80 wr32(wx, WX_SPI_CMD, cmd_val); in wx_fmgr_cmd_op()
180 wr32(wx, WX_MNG_SWFW_SYNC, sem); in wx_acquire_sw_sync()
488 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); in wx_get_mac_addr()
523 wr32(wx, WX_PSR_MAC_SWC_IDX, index); in wx_set_rar()
526 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); in wx_set_rar()
[all …]
/openbmc/linux/drivers/net/ethernet/wangxun/ngbe/
H A Dngbe_mdio.c28 wr32(wx, NGBE_PHY_CONFIG(regnum), value); in ngbe_phy_write_reg_internal()
38 wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF); in ngbe_phy_read_reg_mdi_c22()
43 wr32(wx, WX_MSCA, command); in ngbe_phy_read_reg_mdi_c22()
47 wr32(wx, WX_MSCC, command); in ngbe_phy_read_reg_mdi_c22()
66 wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF); in ngbe_phy_write_reg_mdi_c22()
71 wr32(wx, WX_MSCA, command); in ngbe_phy_write_reg_mdi_c22()
76 wr32(wx, WX_MSCC, command); in ngbe_phy_write_reg_mdi_c22()
93 wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0); in ngbe_phy_read_reg_mdi_c45()
98 wr32(wx, WX_MSCA, command); in ngbe_phy_read_reg_mdi_c45()
102 wr32(wx, WX_MSCC, command); in ngbe_phy_read_reg_mdi_c45()
[all …]
H A Dngbe_main.c167 wr32(wx, WX_GPIO_DDR, WX_GPIO_DDR_0); in ngbe_irq_enable()
168 wr32(wx, WX_GPIO_INTEN, WX_GPIO_INTEN_0 | WX_GPIO_INTEN_1); in ngbe_irq_enable()
169 wr32(wx, WX_GPIO_INTTYPE_LEVEL, 0x0); in ngbe_irq_enable()
170 wr32(wx, WX_GPIO_POLARITY, wx->gpio_ctrl ? 0 : 0x3); in ngbe_irq_enable()
172 wr32(wx, WX_PX_MISC_IEN, mask); in ngbe_irq_enable()
207 wr32(wx, WX_PX_INTA, 1); in ngbe_intr()
331 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); in ngbe_disable_device()
455 wr32(wx, NGBE_PSR_WKUP_CTL, wufc); in ngbe_dev_shutdown()
457 wr32(wx, NGBE_PSR_WKUP_CTL, 0); in ngbe_dev_shutdown()
615 wr32(wx, NGBE_CALSUM_CAP_STATUS, 0x0); in ngbe_probe()
[all …]
H A Dngbe_hw.c44 wr32(wx, NGBE_GPIO_DDR, 0x1); in ngbe_reset_misc()
53 wr32(wx, NGBE_GPIO_DR, swi ? 0 : NGBE_GPIO_DR_0); in ngbe_sfp_modules_txrx_powerctl()
76 wr32(wx, WX_MIS_RST, val | rd32(wx, WX_MIS_RST)); in ngbe_reset_hw()
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c141 wr32(E1000_SYSTIML, ts->tv_nsec); in igb_ptp_write_i210()
142 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); in igb_ptp_write_i210()
203 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); in igb_ptp_adjfine_82576()
223 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfine_82580()
418 wr32(E1000_TSSDP, tssdp); in igb_pin_extts()
419 wr32(E1000_CTRL, ctrl); in igb_pin_extts()
420 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_extts()
484 wr32(E1000_TSSDP, tssdp); in igb_pin_perout()
485 wr32(E1000_CTRL, ctrl); in igb_pin_perout()
486 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_perout()
[all …]
H A De1000_82575.c202 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_init_phy_params_82575()
502 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); in igb_set_sfp_media_type_82575()
548 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_set_sfp_media_type_82575()
666 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_invariants_82575()
872 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
904 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
1060 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d0_lplu_state_82580()
1104 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d3_lplu_state_82580()
1188 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
1213 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
[all …]
H A De1000_mac.c243 wr32(E1000_VLVF(vlvf_index), 0); in igb_vfta_set()
266 wr32(E1000_VLVF(vlvf_index), bits | vlan | E1000_VLVF_VLANID_ENABLE); in igb_vfta_set()
377 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
379 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
716 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
717 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
718 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
720 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
746 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
779 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
[all …]
H A De1000_i210.c64 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); in igb_get_hw_semaphore_i210()
148 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
172 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
250 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
680 wr32(E1000_EECD, flup); in igb_update_flash_i210()
837 wr32(E1000_MDICNFG, reg_val); in igb_pll_workaround_i210()
859 wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST); in igb_pll_workaround_i210()
863 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pll_workaround_i210()
865 wr32(E1000_WUC, 0); in igb_pll_workaround_i210()
867 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
[all …]
H A Digb_main.c588 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
611 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
888 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
905 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
913 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1153 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1493 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1494 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1496 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1499 wr32(E1000_IAM, 0); in igb_irq_disable()
[all …]
H A De1000_mbx.c249 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
307 wr32(E1000_VFLRE, BIT(vf_number)); in igb_check_for_rst_pf()
329 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
357 wr32(E1000_P2VMAILBOX(vf_number), in igb_release_mbx_lock_pf()
392 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
431 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
433 wr32(E1000_P2VMAILBOX(vf_number), in igb_read_mbx_pf()
H A De1000_nvm.c20 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
35 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
66 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
78 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
165 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
178 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
200 wr32(E1000_EECD, eecd); in igb_standby_nvm()
204 wr32(E1000_EECD, eecd); in igb_standby_nvm()
242 wr32(E1000_EECD, eecd); in igb_release_nvm()
263 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c316 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); in i40e_ptp_write()
317 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); in i40e_ptp_write()
358 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); in i40e_ptp_adjfine()
359 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); in i40e_ptp_adjfine()
376 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0); in i40e_ptp_set_1pps_signal_hw()
377 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); in i40e_ptp_set_1pps_signal_hw()
378 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE); in i40e_ptp_set_1pps_signal_hw()
386 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF); in i40e_ptp_set_1pps_signal_hw()
388 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32); in i40e_ptp_set_1pps_signal_hw()
389 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND); in i40e_ptp_set_1pps_signal_hw()
[all …]
H A Di40e_hmc.h112 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
113 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
114 wr32((hw), I40E_PFHMC_SDCMD, val3); \
131 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
132 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
133 wr32((hw), I40E_PFHMC_SDCMD, val3); \
143 wr32((hw), I40E_PFHMC_PDINV, \
H A Di40e_adminq.c270 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
271 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
274 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
276 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
277 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
299 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
300 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
303 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
305 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
306 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
H A Di40e_dcb.c1340 wr32(hw, I40E_PRTDCB_RETSC, reg); in i40e_dcb_hw_rx_fifo_config()
1396 wr32(hw, I40E_PRT_SWR_PM_THR, reg); in i40e_dcb_hw_rx_cmd_monitor_config()
1402 wr32(hw, I40E_PRTDCB_RPPMC, reg); in i40e_dcb_hw_rx_cmd_monitor_config()
1448 wr32(hw, I40E_PRTDCB_MFLCN, reg); in i40e_dcb_hw_pfc_config()
1456 wr32(hw, I40E_PRTDCB_FCCFG, reg); in i40e_dcb_hw_pfc_config()
1463 wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP, reg); in i40e_dcb_hw_pfc_config()
1469 wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP, reg); in i40e_dcb_hw_pfc_config()
1476 wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, reg); in i40e_dcb_hw_pfc_config()
1483 wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, reg); in i40e_dcb_hw_pfc_config()
1493 wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i), reg); in i40e_dcb_hw_pfc_config()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
266 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in iavf_config_asq_regs()
268 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
269 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
295 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in iavf_config_arq_regs()
297 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
298 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in iavf_config_arq_regs()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_sriov.c76 wr32(&pf->hw, GLINT_DYN_CTL(i), GLINT_DYN_CTL_CLEARPBA_M); in ice_free_vf_res()
102 wr32(hw, VPINT_ALLOC(vf->vf_id), 0); in ice_dis_vf_mappings()
103 wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), 0); in ice_dis_vf_mappings()
114 wr32(hw, GLINT_VECT2FUNC(v), reg); in ice_dis_vf_mappings()
118 wr32(hw, VPLAN_TX_QBASE(vf->vf_id), 0); in ice_dis_vf_mappings()
123 wr32(hw, VPLAN_RX_QBASE(vf->vf_id), 0); in ice_dis_vf_mappings()
195 wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); in ice_free_vfs()
293 wr32(hw, VPINT_ALLOC(vf->vf_id), reg); in ice_ena_vf_msix_mappings()
299 wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg); in ice_ena_vf_msix_mappings()
307 wr32(h in ice_ena_vf_msix_mappings()
[all...]
H A Dice_controlq.c276 wr32(hw, ring->head, 0); in ice_cfg_cq_regs()
277 wr32(hw, ring->tail, 0); in ice_cfg_cq_regs()
280 wr32(hw, ring->len, (num_entries | ring->len_ena_mask)); in ice_cfg_cq_regs()
281 wr32(hw, ring->bal, lower_32_bits(ring->desc_buf.pa)); in ice_cfg_cq_regs()
282 wr32(hw, ring->bah, upper_32_bits(ring->desc_buf.pa)); in ice_cfg_cq_regs()
319 wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1)); in ice_cfg_rq_regs()
486 wr32(hw, cq->sq.head, 0); in ice_shutdown_sq()
487 wr32(hw, cq->sq.tail, 0); in ice_shutdown_sq()
488 wr32(hw, cq->sq.len, 0); in ice_shutdown_sq()
489 wr32(hw, cq->sq.bal, 0); in ice_shutdown_sq()
[all …]
/openbmc/linux/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_hw.c61 wr32(wx, TXGBE_TS_CTL, TXGBE_TS_CTL_EVAL_MD); in txgbe_init_thermal_sensor_thresh()
63 wr32(wx, WX_TS_INT_EN, in txgbe_init_thermal_sensor_thresh()
65 wr32(wx, WX_TS_EN, WX_TS_EN_ENA); in txgbe_init_thermal_sensor_thresh()
68 wr32(wx, WX_TS_ALARM_THRE, 677); in txgbe_init_thermal_sensor_thresh()
70 wr32(wx, WX_TS_DALARM_THRE, 614); in txgbe_init_thermal_sensor_thresh()
298 wr32(wx, WX_MIS_RST, val | rd32(wx, WX_MIS_RST)); in txgbe_reset_hw()

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