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Searched refs:wptr_gpu_addr (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_kernel_queue.h71 uint64_t wptr_gpu_addr; member
H A Dkfd_kernel_queue.c123 kq->wptr_gpu_addr = kq->wptr_mem->gpu_addr; in kq_initialize()
138 prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr; in kq_initialize()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mes.h175 uint64_t wptr_gpu_addr; member
185 uint64_t wptr_gpu_addr; member
H A Damdgpu_mes.c550 mqd_prop.wptr_gpu_addr = p->wptr_gpu_addr; in amdgpu_mes_queue_init_mqd()
652 queue_input.wptr_addr = qprops->wptr_gpu_addr; in amdgpu_mes_add_hw_queue()
672 queue->wptr_gpu_addr = qprops->wptr_gpu_addr; in amdgpu_mes_add_hw_queue()
946 props->wptr_gpu_addr = ring->wptr_gpu_addr; in amdgpu_mes_ring_to_queue_props()
H A Damdgpu_ring.c290 ring->wptr_gpu_addr = in amdgpu_ring_init()
660 prop->wptr_gpu_addr = ring->wptr_gpu_addr; in amdgpu_ring_to_mqd_prop()
H A Dsdma_v4_0.c1049 u64 wptr_gpu_addr; in sdma_v4_0_gfx_resume() local
1095 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v4_0_gfx_resume()
1097 lower_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume()
1099 upper_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume()
1134 u64 wptr_gpu_addr; in sdma_v4_0_page_resume() local
1181 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v4_0_page_resume()
1183 lower_32_bits(wptr_gpu_addr)); in sdma_v4_0_page_resume()
1185 upper_32_bits(wptr_gpu_addr)); in sdma_v4_0_page_resume()
H A Dsdma_v4_4_2.c626 u64 wptr_gpu_addr; in sdma_v4_4_2_gfx_resume() local
674 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_4_2_gfx_resume()
676 lower_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_gfx_resume()
678 upper_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_gfx_resume()
714 u64 wptr_gpu_addr; in sdma_v4_4_2_page_resume() local
763 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_4_2_page_resume()
765 lower_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_page_resume()
767 upper_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_page_resume()
H A Dsdma_v5_2.c504 u64 wptr_gpu_addr; in sdma_v5_2_gfx_resume() local
531 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v5_2_gfx_resume()
533 lower_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume()
535 upper_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume()
800 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_2_mqd_init()
H A Dsdma_v6_0.c475 u64 wptr_gpu_addr; in sdma_v6_0_gfx_resume() local
503 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v6_0_gfx_resume()
505 lower_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume()
507 upper_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume()
832 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v6_0_mqd_init()
H A Dsdma_v3_0.c643 u64 wptr_gpu_addr; in sdma_v3_0_gfx_resume() local
706 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v3_0_gfx_resume()
709 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
711 upper_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
H A Dsdma_v5_0.c689 u64 wptr_gpu_addr; in sdma_v5_0_gfx_resume() local
716 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v5_0_gfx_resume()
718 lower_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume()
720 upper_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume()
952 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_0_mqd_init()
H A Dgfx_v11_0.c152 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues()
3243 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume() local
3273 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume()
3275 lower_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3277 upper_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3310 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume()
3312 lower_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3314 upper_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3646 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v11_0_gfx_mqd_init()
3823 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v11_0_compute_mqd_init()
H A Damdgpu_ring.h272 u64 wptr_gpu_addr; member
H A Dgfx_v10_0.c3513 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx10_kiq_map_queues()
6087 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume() local
6120 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume()
6122 lower_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6124 upper_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6157 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume()
6159 lower_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6161 upper_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6397 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v10_0_gfx_mqd_init()
6586 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v10_0_compute_mqd_init()
H A Dgfx_v8_0.c4242 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v8_0_cp_gfx_resume() local
4272 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v8_0_cp_gfx_resume()
4273 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()
4274 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()
4354 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v8_0_kiq_kcq_enable()
4484 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c790 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v9_0_kiq_map_queues()
3102 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v9_0_cp_gfx_resume() local
3130 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v9_0_cp_gfx_resume()
3131 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3132 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3347 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v9_0_mqd_init()
H A Dmes_v10_1.c683 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v10_1_mqd_init()
H A Dmes_v11_0.c763 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v11_0_mqd_init()
H A Damdgpu.h742 uint64_t wptr_gpu_addr; member
H A Dgfx_v7_0.c2913 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v7_0_mqd_init()