| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | xor_regs.h | 183 #define XOR_BASE_ADDR_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ argument
184 (0x250 + ((win_num) * 4)))
185 #define XOR_SIZE_MASK_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ argument
186 (0x270 + ((win_num) * 4)))
187 #define XOR_HIGH_ADDR_REMAP_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ argument
188 (0x290 + ((win_num) * 4)))
189 #define XOR_ADDR_OVRD_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ argument
190 (0x2a0 + ((win_num) * 4)))
193 #define XEXWCR_WIN_EN_OFFS(win_num) (win_num) argument
194 #define XEXWCR_WIN_EN_MASK(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) argument
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| H A D | xor.h | 86 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
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| /openbmc/linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil.c | 136 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, in program_ib_windows() argument
142 if (win_num >= pcie->ppio_wins) { in program_ib_windows()
148 value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num)); in program_ib_windows()
152 mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num)); in program_ib_windows()
155 PAB_EXT_PEX_AMAP_SIZEN(win_num)); in program_ib_windows()
158 PAB_PEX_AMAP_AXI_WIN(win_num)); in program_ib_windows()
160 PAB_EXT_PEX_AMAP_AXI_WIN(win_num)); in program_ib_windows()
163 PAB_PEX_AMAP_PEX_WIN_L(win_num)); in program_ib_windows()
165 PAB_PEX_AMAP_PEX_WIN_H(win_num)); in program_ib_windows()
173 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, in program_ob_windows() argument
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| H A D | pcie-mobiveil.h | 183 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
185 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pci-aardvark.c | 454 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
459 lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); in advk_pcie_set_ob_win()
460 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
461 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
462 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
463 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
464 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
465 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
468 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
470 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
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| /openbmc/qemu/hw/display/ |
| H A D | exynos4210_fimd.c | 1076 int win_num, uint32_t val) in exynos4210_fimd_trace_bppmode() argument
1078 Exynos4210fimdWindow *w = &s->window[win_num]; in exynos4210_fimd_trace_bppmode()
1082 win_num, w->winmap & 0xFFFFFF); in exynos4210_fimd_trace_bppmode()
1089 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num, in exynos4210_fimd_trace_bppmode()
1094 int win_num, uint32_t val) in exynos4210_fimd_trace_bppmode() argument
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| /openbmc/linux/drivers/net/ethernet/3com/ |
| H A D | 3c589_cs.c | 67 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) argument
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| H A D | 3c574_cs.c | 131 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) argument
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| H A D | 3c509.c | 116 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) argument
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| H A D | 3c515.c | 171 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) argument
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| /openbmc/linux/drivers/net/ethernet/amd/ |
| H A D | nmclan_cs.c | 291 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) argument
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