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Searched refs:vxrm (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dvector_helper.c2139 CPURISCVState *env, int vxrm);
2144 CPURISCVState *env, int vxrm) \
2148 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1); \
2154 uint32_t vl, uint32_t vm, int vxrm, in vext_vv_rm_1() argument
2165 fn(vd, vs1, vs2, i, env, vxrm); in vext_vv_rm_1()
2182 switch (env->vxrm) { in vext_vv_rm_2()
2213 static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, in saddu8() argument
2224 static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, in saddu16() argument
2235 static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, in saddu32() argument
2246 static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a, in saddu64() argument
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H A Dmachine.c143 VMSTATE_UINTTL(env.vxrm, RISCVCPU),
H A Dcpu.h203 target_ulong vxrm; member
H A Dcsr.c752 *val = env->vxrm; in read_vxrm()
762 env->vxrm = val; in write_vxrm()
807 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); in read_vcsr()
817 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; in write_vcsr()