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Searched refs:vsew (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc553 MemOp vsew, RISCVVlmul vlmul)
555 return vma << 7 | vta << 6 | vsew << 3 | vlmul;
739 static void set_vtype(TCGContext *s, TCGType type, MemOp vsew)
741 const VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew];
744 s->riscv_cur_vsew = vsew;
760 static void set_vtype_len_sew(TCGContext *s, TCGType type, MemOp vsew)
762 if (type != s->riscv_cur_type || vsew != s->riscv_cur_vsew) {
763 set_vtype(s, type, vsew);
2848 static void probe_frac_lmul_1(TCGType type, MemOp vsew)
2850 VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew];
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/openbmc/qemu/target/riscv/
H A Dcpu.h759 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, in vext_get_vlmax() argument
769 return vlen >> (vsew + 3 - lmul); in vext_get_vlmax()
H A Dcpu_helper.c145 uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); in cpu_get_tb_cpu_state() local
146 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in cpu_get_tb_cpu_state()
147 uint32_t maxsz = vlmax << vsew; in cpu_get_tb_cpu_state()
151 flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); in cpu_get_tb_cpu_state()
H A Dvector_helper.c40 uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW); in HELPER() local
41 uint16_t sew = 8 << vsew; in HELPER()
75 vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in HELPER()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc3565 * Whole Vector Register Move Instructions depend on vtype register(vsew).