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Searched refs:val64 (Results 1 – 25 of 120) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/neterion/
H A Ds2io.c120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ argument
1010 register u64 val64 = 0; in s2io_verify_pci_mode() local
1013 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1014 mode = (u8)GET_PCI_MODE(val64); in s2io_verify_pci_mode()
1016 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_verify_pci_mode()
1044 register u64 val64 = 0; in s2io_print_pci_mode() local
1049 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1050 mode = (u8)GET_PCI_MODE(val64); in s2io_print_pci_mode()
1052 if (val64 & PCI_MODE_UNKNOWN_MODE) in s2io_print_pci_mode()
1094 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); in s2io_print_pci_mode()
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/openbmc/qemu/hw/misc/
H A Dxlnx-versal-crl.c35 static void crl_status_postw(RegisterInfo *reg, uint64_t val64) in crl_status_postw() argument
41 static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) in crl_enable_prew() argument
44 uint32_t val = val64; in crl_enable_prew()
51 static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) in crl_disable_prew() argument
54 uint32_t val = val64; in crl_disable_prew()
87 static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) in crl_rst_r5_prew() argument
91 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); in crl_rst_r5_prew()
92 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); in crl_rst_r5_prew()
93 return val64; in crl_rst_r5_prew()
96 static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) in crl_rst_adma_prew() argument
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H A Dsifive_e_prci.c47 uint64_t val64, unsigned int size) in sifive_e_prci_write() argument
52 s->hfrosccfg = (uint32_t) val64; in sifive_e_prci_write()
57 s->hfxosccfg = (uint32_t) val64; in sifive_e_prci_write()
62 s->pllcfg = (uint32_t) val64; in sifive_e_prci_write()
67 s->plloutdiv = (uint32_t) val64; in sifive_e_prci_write()
71 __func__, (int)addr, (int)val64); in sifive_e_prci_write()
H A Dxlnx-versal-trng.c285 static void trng_isr_postw(RegisterInfo *reg, uint64_t val64) in trng_isr_postw() argument
291 static uint64_t trng_ier_prew(RegisterInfo *reg, uint64_t val64) in trng_ier_prew() argument
294 uint32_t val = val64; in trng_ier_prew()
301 static uint64_t trng_idr_prew(RegisterInfo *reg, uint64_t val64) in trng_idr_prew() argument
304 uint32_t val = val64; in trng_idr_prew()
333 static void trng_int_ctrl_postw(RegisterInfo *reg, uint64_t val64) in trng_int_ctrl_postw() argument
336 uint32_t v32 = val64; in trng_int_ctrl_postw()
397 static void trng_ctrl_postw(RegisterInfo *reg, uint64_t val64) in trng_ctrl_postw() argument
405 if (FIELD_EX32(val64, CTRL, PRNGSRST)) { in trng_ctrl_postw()
411 if (!FIELD_EX32(val64, CTRL, PRNGSTART)) { in trng_ctrl_postw()
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H A Dxlnx-zynqmp-crf.c31 static void ir_status_postw(RegisterInfo *reg, uint64_t val64) in ir_status_postw() argument
37 static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) in ir_enable_prew() argument
40 uint32_t val = val64; in ir_enable_prew()
47 static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) in ir_disable_prew() argument
50 uint32_t val = val64; in ir_disable_prew()
57 static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64) in rst_fpd_apu_prew() argument
60 uint32_t val = val64; in rst_fpd_apu_prew()
75 return val64; in rst_fpd_apu_prew()
H A Dstm32l4x5_exti.c177 uint64_t val64, unsigned int size) in stm32l4x5_exti_write() argument
182 trace_stm32l4x5_exti_write(addr, val64); in stm32l4x5_exti_write()
187 s->imr[bank] = val64 & valid_mask(bank); in stm32l4x5_exti_write()
191 s->emr[bank] = val64 & valid_mask(bank); in stm32l4x5_exti_write()
195 s->rtsr[bank] = val64 & configurable_mask(bank); in stm32l4x5_exti_write()
199 s->ftsr[bank] = val64 & configurable_mask(bank); in stm32l4x5_exti_write()
203 const uint32_t set = val64 & configurable_mask(bank); in stm32l4x5_exti_write()
217 const uint32_t cleared = s->pr[bank] & val64 & configurable_mask(bank); in stm32l4x5_exti_write()
H A Dsifive_test.c36 uint64_t val64, unsigned int size) in sifive_test_write() argument
39 int status = val64 & 0xffff; in sifive_test_write()
40 int code = (val64 >> 16) & 0xffff; in sifive_test_write()
58 __func__, (int)addr, val64); in sifive_test_write()
H A Dxlnx-versal-xramc.c29 static void xram_isr_postw(RegisterInfo *reg, uint64_t val64) in xram_isr_postw() argument
35 static uint64_t xram_ien_prew(RegisterInfo *reg, uint64_t val64) in xram_ien_prew() argument
38 uint32_t val = val64; in xram_ien_prew()
45 static uint64_t xram_ids_prew(RegisterInfo *reg, uint64_t val64) in xram_ids_prew() argument
48 uint32_t val = val64; in xram_ids_prew()
H A Dxlnx-zynqmp-apu-ctrl.c77 static void isr_postw(RegisterInfo *reg, uint64_t val64) in isr_postw() argument
83 static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64) in ien_prew() argument
86 uint32_t val = val64; in ien_prew()
93 static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64) in ids_prew() argument
96 uint32_t val = val64; in ids_prew()
/openbmc/qemu/hw/nvram/
H A Dxlnx-bbram.c205 static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64) in bbram_ctrl_postw() argument
208 uint32_t val = val64; in bbram_ctrl_postw()
217 static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64) in bbram_pgm_mode_postw() argument
220 uint32_t val = val64; in bbram_pgm_mode_postw()
230 static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64) in bbram_aes_crc_postw() argument
256 static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64) in bbram_key_prew() argument
262 return val64; in bbram_key_prew()
271 static void bbram_key_postw(RegisterInfo *reg, uint64_t val64) in bbram_key_postw() argument
295 static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64) in bbram_r8_prew() argument
300 val64 = *(uint32_t *)reg->data; in bbram_r8_prew()
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H A Dxlnx-versal-efuse-ctrl.c233 static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64) in efuse_isr_postw() argument
239 static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64) in efuse_ier_prew() argument
242 uint32_t val = val64; in efuse_ier_prew()
249 static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64) in efuse_idr_prew() argument
252 uint32_t val = val64; in efuse_idr_prew()
424 static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64) in efuse_pgm_addr_postw() argument
427 unsigned bit = val64; in efuse_pgm_addr_postw()
466 static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64) in efuse_rd_addr_postw() argument
469 unsigned bit = val64; in efuse_rd_addr_postw()
500 static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64) in efuse_cache_load_prew() argument
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/openbmc/qemu/hw/rtc/
H A Dxlnx-zynqmp-rtc.c63 static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) in current_time_postr() argument
70 static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) in rtc_int_status_postw() argument
76 static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) in rtc_int_en_prew() argument
80 s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; in rtc_int_en_prew()
85 static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) in rtc_int_dis_prew() argument
89 s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; in rtc_int_dis_prew()
94 static void addr_error_postw(RegisterInfo *reg, uint64_t val64) in addr_error_postw() argument
100 static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) in addr_error_int_en_prew() argument
104 s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; in addr_error_int_en_prew()
109 static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) in addr_error_int_dis_prew() argument
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/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-config.c27 *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64; in cscfg_set_reg()
47 reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval); in cscfg_save_reg()
65 param_csdev->val64 = reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT; in cscfg_init_reg_param()
67 if (param_csdev->val64) in cscfg_init_reg_param()
68 reg_csdev->reg_desc.val64 = param_csdev->current_value; in cscfg_init_reg_param()
130 reg_csdev->reg_desc.val64 = reg_desc->val64; in cscfg_reset_feat()
169 if (param_csdev->val64) { in cscfg_update_presets()
172 param_csdev->reg_csdev->reg_desc.val64 = val; in cscfg_update_presets()
208 if (param_csdev->val64) { in cscfg_update_curr_params()
211 param_csdev->reg_csdev->reg_desc.val64 = val; in cscfg_update_curr_params()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dgtt.c156 memcpy(&(e)->val64, &v, sizeof(v)); \
314 &e->val64, 8); in gtt_get_entry64()
318 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index); in gtt_get_entry64()
320 e->val64 = *((u64 *)pt + index); in gtt_get_entry64()
339 &e->val64, 8); in gtt_set_entry64()
343 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64); in gtt_set_entry64()
345 *((u64 *)pt + index) = e->val64; in gtt_set_entry64()
367 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT; in gen8_gtt_get_pfn()
369 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT; in gen8_gtt_get_pfn()
371 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT; in gen8_gtt_get_pfn()
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/openbmc/qemu/hw/intc/
H A Dxlnx-zynqmp-ipi.c176 static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64) in xlnx_zynqmp_ipi_trig_prew() argument
180 xlnx_zynqmp_ipi_set_trig(s, val64); in xlnx_zynqmp_ipi_trig_prew()
182 return val64; in xlnx_zynqmp_ipi_trig_prew()
185 static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64) in xlnx_zynqmp_ipi_trig_postw() argument
197 static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64) in xlnx_zynqmp_ipi_isr_prew() argument
201 xlnx_zynqmp_ipi_set_obs(s, val64); in xlnx_zynqmp_ipi_isr_prew()
203 return val64; in xlnx_zynqmp_ipi_isr_prew()
206 static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64) in xlnx_zynqmp_ipi_isr_postw() argument
213 static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64) in xlnx_zynqmp_ipi_ier_prew() argument
216 uint32_t val = val64; in xlnx_zynqmp_ipi_ier_prew()
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/openbmc/linux/drivers/iio/imu/inv_icm42600/
H A Dinv_icm42600_accel.c362 int64_t val64; in inv_icm42600_accel_read_offset() local
420 val64 = (int64_t)offset * 5LL * 9806650LL; in inv_icm42600_accel_read_offset()
422 if (val64 >= 0) in inv_icm42600_accel_read_offset()
423 val64 += 10000LL / 2LL; in inv_icm42600_accel_read_offset()
425 val64 -= 10000LL / 2LL; in inv_icm42600_accel_read_offset()
426 bias = div_s64(val64, 10000L); in inv_icm42600_accel_read_offset()
438 int64_t val64; in inv_icm42600_accel_write_offset() local
466 val64 = (int64_t)val * 1000000LL + (int64_t)val2; in inv_icm42600_accel_write_offset()
467 if (val64 < min || val64 > max) in inv_icm42600_accel_write_offset()
477 val64 = val64 * 10000LL; in inv_icm42600_accel_write_offset()
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H A Dinv_icm42600_gyro.c374 int64_t val64; in inv_icm42600_gyro_read_offset() local
432 val64 = (int64_t)offset * 64LL * 3141592653LL; in inv_icm42600_gyro_read_offset()
434 if (val64 >= 0) in inv_icm42600_gyro_read_offset()
435 val64 += 2048 * 180 / 2; in inv_icm42600_gyro_read_offset()
437 val64 -= 2048 * 180 / 2; in inv_icm42600_gyro_read_offset()
438 bias = div_s64(val64, 2048 * 180); in inv_icm42600_gyro_read_offset()
450 int64_t val64, min, max; in inv_icm42600_gyro_write_offset() local
477 val64 = (int64_t)val * 1000000000LL + (int64_t)val2; in inv_icm42600_gyro_write_offset()
478 if (val64 < min || val64 > max) in inv_icm42600_gyro_write_offset()
488 val64 = val64 * 180LL * 2048LL; in inv_icm42600_gyro_write_offset()
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/openbmc/linux/arch/mips/include/asm/
H A Dmips-cps.h26 uint64_t val64; \
36 val64 = __raw_readl(addr_##unit##_##name() + 4); \
37 val64 <<= 32; \
38 val64 |= __raw_readl(addr_##unit##_##name()); \
39 return val64; \
/openbmc/linux/lib/zstd/common/
H A Dmem.h70 MEM_STATIC void MEM_writeLE64(void* memPtr, U64 val64);
79 MEM_STATIC void MEM_writeBE64(void* memPtr, U64 val64);
184 MEM_STATIC void MEM_writeLE64(void *memPtr, U64 val64) in MEM_writeLE64() argument
186 put_unaligned_le64(val64, memPtr); in MEM_writeLE64()
222 MEM_STATIC void MEM_writeBE64(void *memPtr, U64 val64) in MEM_writeBE64() argument
224 put_unaligned_be64(val64, memPtr); in MEM_writeBE64()
/openbmc/qemu/tests/tcg/arm/
H A Dcommpage.c48 int64_t val64 = 1; in main() local
58 fail_unless(ARM_KUSER_CMPXCHG64(&oldval, &newval, &val64) == 0); in main()
59 printf("val64 = %lld\n", val64); in main()
/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.h308 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
309 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
329 u64 val64; in OCTEP_PCI_WIN_READ() local
333 val64 = readq(oct->pci_win_regs.pci_win_rd_data); in OCTEP_PCI_WIN_READ()
336 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); in OCTEP_PCI_WIN_READ()
338 return val64; in OCTEP_PCI_WIN_READ()
/openbmc/qemu/hw/pci-host/
H A Di440fx.c143 uint64_t val64; in i440fx_pcihost_get_pci_hole_start() local
146 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); in i440fx_pcihost_get_pci_hole_start()
147 value = val64; in i440fx_pcihost_get_pci_hole_start()
148 assert(value == val64); in i440fx_pcihost_get_pci_hole_start()
157 uint64_t val64; in i440fx_pcihost_get_pci_hole_end() local
160 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; in i440fx_pcihost_get_pci_hole_end()
161 value = val64; in i440fx_pcihost_get_pci_hole_end()
162 assert(value == val64); in i440fx_pcihost_get_pci_hole_end()
/openbmc/qemu/hw/usb/
H A Dxlnx-versal-usb2-ctrl-regs.c81 static void ir_status_postw(RegisterInfo *reg, uint64_t val64) in ir_status_postw() argument
91 static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) in ir_enable_prew() argument
94 uint32_t val = val64; in ir_enable_prew()
101 static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) in ir_disable_prew() argument
104 uint32_t val = val64; in ir_disable_prew()
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dpio_copy.c108 val.val64 = 0; in pio_copy()
110 writeq(val.val64, dest); in pio_copy()
186 pbuf->carry.val64 = 0; in read_low_bytes()
223 temp = pbuf->carry.val64 | (new << mshift(pbuf->carry_bytes)); in merge_write8()
225 pbuf->carry.val64 = new >> zshift(pbuf->carry_bytes); in merge_write8()
233 writeq(carry.val64, dest); in carry8_write8()
245 writeq(pbuf->carry.val64, dest); in carry_write8()
/openbmc/qemu/hw/char/
H A Dsifive_uart.c173 uint64_t val64, unsigned int size) in sifive_uart_write() argument
176 uint32_t value = val64; in sifive_uart_write()
184 s->ie = val64; in sifive_uart_write()
188 s->txctrl = val64; in sifive_uart_write()
191 s->rxctrl = val64; in sifive_uart_write()
194 s->div = val64; in sifive_uart_write()

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