Home
last modified time | relevance | path

Searched refs:uncached_cpsr (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c295 env->uncached_cpsr ^= CPSR_E; in HELPER()
569 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { in HELPER()
584 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { in HELPER()
593 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER()
602 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER()
610 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER()
625 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
689 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { in HELPER()
728 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { in HELPER()
H A Dhflags.c183 if (env->uncached_cpsr & CPSR_IL) { in rebuild_hflags_a32()
/openbmc/qemu/linux-user/arm/
H A Dcpu_loop.c531 env->uncached_cpsr |= CPSR_E; in target_cpu_copy_regs()
/openbmc/qemu/hw/arm/
H A Dboot.c705 env->uncached_cpsr &= ~CPSR_E; in do_cpu_reset()
712 env->uncached_cpsr |= CPSR_E; in do_cpu_reset()
/openbmc/qemu/target/arm/
H A Dhelper.c275 return env->uncached_cpsr & CPSR_PAN; in arm_pan_enabled()
10473 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || in bad_mode_switch()
10496 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && in bad_mode_switch()
10514 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | in cpsr_read()
10612 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { in cpsr_write()
10613 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { in cpsr_write()
10640 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
10647 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
10653 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); in cpsr_write()
10688 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()
[all …]
H A Dcpu.h239 uint32_t uncached_cpsr; member
2509 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2707 switch (env->uncached_cpsr & 0x1f) { in arm_current_el()
3047 return env->uncached_cpsr & CPSR_E; in arm_cpu_data_is_big_endian_a32()
H A Dcpu.c357 env->uncached_cpsr = ARM_CPU_MODE_USR; in arm_cpu_reset_hold()
374 env->uncached_cpsr = ARM_CPU_MODE_HYP; in arm_cpu_reset_hold()
376 env->uncached_cpsr = ARM_CPU_MODE_SVC; in arm_cpu_reset_hold()
H A Dkvm.c2128 i = bank_number(env->uncached_cpsr & CPSR_M); in kvm_arch_put_registers()
2321 i = bank_number(env->uncached_cpsr & CPSR_M); in kvm_arch_get_registers()