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Searched refs:tx_fifo (Results 1 – 25 of 66) sorted by relevance

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/openbmc/qemu/hw/char/
H A Dsifive_uart.c79 fifo8_reset(&s->tx_fifo); in sifive_uart_xmit()
83 if (fifo8_is_empty(&s->tx_fifo)) { in sifive_uart_xmit()
88 characters = fifo8_peek_bufptr(&s->tx_fifo, in sifive_uart_xmit()
89 fifo8_num_used(&s->tx_fifo), &numptr); in sifive_uart_xmit()
94 fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); in sifive_uart_xmit()
97 if (!fifo8_is_empty(&s->tx_fifo)) { in sifive_uart_xmit()
101 fifo8_reset(&s->tx_fifo); in sifive_uart_xmit()
107 if (!fifo8_is_full(&s->tx_fifo)) { in sifive_uart_xmit()
120 if (size > fifo8_num_free(&s->tx_fifo)) { in sifive_uart_write_tx_fifo()
121 size = fifo8_num_free(&s->tx_fifo); in sifive_uart_write_tx_fifo()
[all …]
H A Dibex_uart.c162 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); in ibex_uart_xmit()
166 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); in ibex_uart_xmit()
210 memcpy(s->tx_fifo + s->tx_level, buf, size); in uart_write_tx_fifo()
492 VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
/openbmc/qemu/hw/ssi/
H A Dpl022.c102 val = s->tx_fifo[i]; in pl022_xfer()
184 s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; in pl022_write()
239 s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) || in pl022_post_load()
264 VMSTATE_UINT16(tx_fifo[0], PL022State),
266 VMSTATE_UINT16(tx_fifo[1], PL022State),
268 VMSTATE_UINT16(tx_fifo[2], PL022State),
270 VMSTATE_UINT16(tx_fifo[3], PL022State),
272 VMSTATE_UINT16(tx_fifo[4], PL022State),
274 VMSTATE_UINT16(tx_fifo[5], PL022State),
276 VMSTATE_UINT16(tx_fifo[6], PL022State),
[all …]
H A Dimx_spi.c66 VMSTATE_FIFO32(tx_fifo, IMXSPIState),
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
105 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_update_irq()
111 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_update_irq()
168 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
170 while (!fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
183 tx = fifo32_pop(&s->tx_fifo); in imx_spi_flush_txfifo()
224 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
232 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
362 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_write()
[all …]
H A Dbcm2835_spi.c74 if (fifo8_is_full(&s->tx_fifo)) { in bcm2835_spi_update_tx_flags()
81 if (fifo8_is_empty(&s->tx_fifo) && s->cs & BCM2835_SPI_CS_TA) { in bcm2835_spi_update_tx_flags()
92 while (!fifo8_is_empty(&s->tx_fifo) && !fifo8_is_full(&s->rx_fifo)) { in bcm2835_spi_flush_tx_fifo()
93 tx_byte = fifo8_pop(&s->tx_fifo); in bcm2835_spi_flush_tx_fifo()
161 fifo8_reset(&s->tx_fifo); in bcm2835_spi_write()
191 fifo8_push(&s->tx_fifo, value & 0xff); in bcm2835_spi_write()
233 fifo8_create(&s->tx_fifo, FIFO_SIZE); in bcm2835_spi_realize()
240 fifo8_reset(&s->tx_fifo); in bcm2835_spi_reset()
256 VMSTATE_FIFO8(tx_fifo, BCM2835SPIState),
H A Dallwinner-a10-spi.c175 fifo8_reset(&s->tx_fifo); in allwinner_a10_spi_txfifo_reset()
248 if (fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_update_irq()
254 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 2)) { in allwinner_a10_spi_update_irq()
260 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 1)) { in allwinner_a10_spi_update_irq()
266 if (fifo8_num_used(&s->tx_fifo) <= (AW_A10_SPI_FIFO_SIZE >> 2)) { in allwinner_a10_spi_update_irq()
292 trace_allwinner_a10_spi_flush_txfifo_begin(fifo8_num_used(&s->tx_fifo), in allwinner_a10_spi_flush_txfifo()
295 while (!fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_flush_txfifo()
296 uint8_t tx = fifo8_pop(&s->tx_fifo); in allwinner_a10_spi_flush_txfifo()
335 if (fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_flush_txfifo()
340 trace_allwinner_a10_spi_flush_txfifo_end(fifo8_num_used(&s->tx_fifo), in allwinner_a10_spi_flush_txfifo()
[all …]
H A Dsifive_spi.c64 fifo8_reset(&s->tx_fifo); in sifive_spi_txfifo_reset()
93 if (fifo8_num_used(&s->tx_fifo) < s->regs[R_TXMARK]) { in sifive_spi_update_irq()
135 while (!fifo8_is_empty(&s->tx_fifo)) { in sifive_spi_flush_txfifo()
136 tx = fifo8_pop(&s->tx_fifo); in sifive_spi_flush_txfifo()
194 if (fifo8_is_full(&s->tx_fifo)) { in sifive_spi_read()
261 if (!fifo8_is_full(&s->tx_fifo)) { in sifive_spi_write()
262 fifo8_push(&s->tx_fifo, (uint8_t)value); in sifive_spi_write()
327 fifo8_create(&s->tx_fifo, FIFO_CAPACITY); in sifive_spi_realize()
H A Dmss-spi.c89 fifo32_reset(&s->tx_fifo); in txfifo_reset()
230 while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { in spi_flush_txfifo()
235 tx = fifo32_pop(&s->tx_fifo); in spi_flush_txfifo()
279 if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
283 fifo32_push(&s->tx_fifo, value); in spi_write()
284 if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) { in spi_write()
286 } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
385 fifo32_create(&s->tx_fifo, FIFO_CAPACITY); in mss_spi_realize()
394 VMSTATE_FIFO32(tx_fifo, MSSSpiState),
H A Dxilinx_spips.c308 fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_update_cs_lines()
322 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | in xilinx_spips_update_ixr()
323 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | in xilinx_spips_update_ixr()
324 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); in xilinx_spips_update_ixr()
617 if (fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_flush_txfifo()
623 if (!fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_flush_txfifo()
624 tx_rx[i] = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
629 tx = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
638 tx = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
764 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { in xilinx_spips_check_zero_pump()
[all …]
H A Dxilinx_spi.c97 Fifo8 tx_fifo; member
104 fifo8_reset(&s->tx_fifo); in txfifo_reset()
179 while (!fifo8_is_empty(&s->tx_fifo)) { in spi_flush_txfifo()
180 tx = (uint32_t)fifo8_pop(&s->tx_fifo); in spi_flush_txfifo()
261 fifo8_push(&s->tx_fifo, (uint8_t)value); in spi_write()
262 if (fifo8_is_full(&s->tx_fifo)) { in spi_write()
348 fifo8_create(&s->tx_fifo, FIFO_CAPACITY); in xilinx_spi_realize()
357 VMSTATE_FIFO8(tx_fifo, XilinxSPI),
H A Dxlnx-versal-ospi.c633 while (!fifo8_is_empty(&s->tx_fifo)) { in ospi_flush_txfifo()
634 uint32_t tx_rx = fifo8_pop(&s->tx_fifo); in ospi_flush_txfifo()
647 fifo8_push(&s->tx_fifo, flash_addr >> 24); in ospi_tx_fifo_push_address_raw()
650 fifo8_push(&s->tx_fifo, flash_addr >> 16); in ospi_tx_fifo_push_address_raw()
653 fifo8_push(&s->tx_fifo, flash_addr >> 8); in ospi_tx_fifo_push_address_raw()
655 fifo8_push(&s->tx_fifo, flash_addr); in ospi_tx_fifo_push_address_raw()
678 fifo8_reset(&s->tx_fifo); in ospi_tx_fifo_push_rd_op_addr()
681 fifo8_push(&s->tx_fifo, inst_code); in ospi_tx_fifo_push_rd_op_addr()
696 fifo8_push(&s->tx_fifo, data >> shift); in ospi_tx_fifo_push_stig_wr_data()
713 fifo8_push(&s->tx_fifo, 0); in ospi_tx_fifo_push_stig_rd_data()
[all …]
H A Dibex_spi_host.c124 fifo8_reset(&s->tx_fifo); in ibex_spi_txfifo_reset()
246 if (fifo8_is_empty(&s->tx_fifo)) { in ibex_spi_host_transfer()
255 tx = fifo8_pop(&s->tx_fifo); in ibex_spi_host_transfer()
277 data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4); in ibex_spi_host_transfer()
463 if (fifo8_is_full(&s->tx_fifo)) { in ibex_spi_host_write()
482 fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); in ibex_spi_host_write()
578 VMSTATE_FIFO8(tx_fifo, IbexSPIHostState),
611 fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN); in ibex_spi_host_realize()
/openbmc/qemu/hw/net/
H A Dstellaris_enet.c75 uint8_t tx_fifo[2048]; member
124 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) { in stellaris_enet_post_load()
148 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
167 return s->tx_fifo[0] | (s->tx_fifo[1] << 8); in stellaris_txpacket_datalen()
186 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo)); in stellaris_txpacket_complete()
210 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen); in stellaris_enet_send()
219 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2); in stellaris_enet_send()
220 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen); in stellaris_enet_send()
402 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) { in stellaris_enet_write()
403 s->tx_fifo[s->tx_fifo_len++] = value; in stellaris_enet_write()
[all …]
H A Dallwinner_emac.c149 fifo8_reset(&s->tx_fifo[chan]); in aw_emac_tx_reset()
343 fifo = &s->tx_fifo[chan]; in aw_emac_write()
376 fifo = &s->tx_fifo[s->tx_channel]; in aw_emac_write()
461 fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE); in aw_emac_realize()
462 fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE); in aw_emac_realize()
510 VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1,
/openbmc/linux/drivers/net/ethernet/google/gve/
H A Dgve_tx.c187 gve_tx_free_fifo(&tx->tx_fifo, space_freed); in gve_clean_xdp_done()
221 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_free_ring()
222 gve_unassign_qpl(priv, tx->tx_fifo.qpl->id); in gve_tx_free_ring()
223 tx->tx_fifo.qpl = NULL; in gve_tx_free_ring()
265 tx->tx_fifo.qpl = gve_assign_tx_qpl(priv, idx); in gve_tx_alloc_ring()
266 if (!tx->tx_fifo.qpl) in gve_tx_alloc_ring()
269 if (gve_tx_fifo_init(priv, &tx->tx_fifo)) in gve_tx_alloc_ring()
291 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_alloc_ring()
294 gve_unassign_qpl(priv, tx->tx_fifo.qpl->id); in gve_tx_alloc_ring()
358 pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, in gve_skb_fifo_bytes_required()
[all …]
/openbmc/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c60 struct netup_i2c_fifo_regs tx_fifo; member
103 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
104 writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
125 writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_reset()
127 writew(0x800, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_reset()
135 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); in netup_i2c_fifo_tx()
141 writeb(data, &i2c->regs->tx_fifo.data8); in netup_i2c_fifo_tx()
148 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
149 &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_fifo_tx()
/openbmc/qemu/hw/i3c/
H A Dremote-i3c.c54 Fifo8 tx_fifo; member
89 return !fifo8_is_empty(&i3c->tx_fifo); in remote_i3c_tx_in_progress()
95 uint32_t num_bytes = fifo8_num_used(&i3c->tx_fifo); in remote_i3c_chr_send_bytes()
103 buf[i] = fifo8_pop(&i3c->tx_fifo); in remote_i3c_chr_send_bytes()
127 if (fifo8_num_free(&i3c->tx_fifo) < num_to_send) { in remote_i3c_tx_fifo_push()
130 num_to_push = fifo8_num_free(&i3c->tx_fifo); in remote_i3c_tx_fifo_push()
136 fifo8_push(&i3c->tx_fifo, data[i]); in remote_i3c_tx_fifo_push()
425 fifo8_create(&i3c->tx_fifo, i3c->cfg.buf_size); in remote_i3c_realize()
/openbmc/linux/drivers/usb/mtu3/
H A Dmtu3_core.c543 struct mtu3_fifo_info *tx_fifo; in get_ep_fifo_config() local
549 tx_fifo = &mtu->tx_fifo; in get_ep_fifo_config()
550 tx_fifo->base = 0; in get_ep_fifo_config()
551 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; in get_ep_fifo_config()
552 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); in get_ep_fifo_config()
562 tx_fifo = &mtu->tx_fifo; in get_ep_fifo_config()
563 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE; in get_ep_fifo_config()
564 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1; in get_ep_fifo_config()
565 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); in get_ep_fifo_config()
569 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT; in get_ep_fifo_config()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_xuartlite.c27 unsigned int tx_fifo; member
44 out_be32(&regs->tx_fifo, ch & 0xff); in uartlite_serial_putc()
134 out_be32(&regs->tx_fifo, ch & 0xff); in _debug_uart_putc()
/openbmc/u-boot/drivers/spi/
H A Dpic32_spi.c79 void (*tx_fifo)(struct pic32_spi_priv *); member
167 priv->tx_fifo = pic32_spi_tx_byte; in pic32_spi_set_word_size()
172 priv->tx_fifo = pic32_spi_tx_word; in pic32_spi_set_word_size()
177 priv->tx_fifo = pic32_spi_tx_dword; in pic32_spi_set_word_size()
266 priv->tx_fifo(priv); in pic32_spi_xfer()
/openbmc/linux/drivers/mailbox/
H A Domap-mailbox.c108 struct omap_mbox_fifo tx_fifo; member
153 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write()
167 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_full()
176 &mbox->tx_fifo : &mbox->rx_fifo; in ack_mbox_irq()
189 &mbox->tx_fifo : &mbox->rx_fifo; in is_mbox_irq()
204 &mbox->tx_fifo : &mbox->rx_fifo; in _omap_mbox_enable_irq()
216 &mbox->tx_fifo : &mbox->rx_fifo; in _omap_mbox_disable_irq()
791 fifo = &mbox->tx_fifo; in omap_mbox_probe()
/openbmc/linux/drivers/staging/pi433/
H A Dpi433_if.c83 STRUCT_KFIFO_REC_1(MSG_FIFO_SIZE) tx_fifo;
572 (!kfifo_is_empty(&device->tx_fifo) || in pi433_tx_thread()
583 retval = kfifo_out(&device->tx_fifo, &tx_cfg, sizeof(tx_cfg)); in pi433_tx_thread()
591 retval = kfifo_out(&device->tx_fifo, &size, sizeof(size_t)); in pi433_tx_thread()
628 retval = kfifo_out(&device->tx_fifo, &device->buffer[position], in pi433_tx_thread()
750 if (kfifo_is_empty(&device->tx_fifo)) { in pi433_tx_thread()
847 available = kfifo_avail(&device->tx_fifo); in pi433_write()
855 retval = kfifo_in(&device->tx_fifo, &instance->tx_cfg, in pi433_write()
860 retval = kfifo_in(&device->tx_fifo, &count, sizeof(size_t)); in pi433_write()
864 retval = kfifo_from_user(&device->tx_fifo, buf, count, &copied); in pi433_write()
[all …]
/openbmc/linux/drivers/net/can/usb/
H A Ducan.c152 u8 tx_fifo; /* Size of the transmission fifo */ member
270 u8 tx_fifo; member
333 up->context_array = kcalloc(up->device_info.tx_fifo, in ucan_alloc_context_array()
342 for (i = 0; i < up->device_info.tx_fifo; i++) { in ucan_alloc_context_array()
348 up->available_tx_urbs = up->device_info.tx_fifo; in ucan_alloc_context_array()
365 for (i = 0; i < up->device_info.tx_fifo; i++) { in ucan_alloc_context()
453 up->device_info.tx_fifo = device_info->tx_fifo; in ucan_parse_device_info()
654 if (echo_index >= up->device_info.tx_fifo) { in ucan_tx_complete_msg()
1476 if (ctl_msg_buffer->cmd_get_device_info.tx_fifo == 0) { in ucan_probe()
1492 ctl_msg_buffer->cmd_get_device_info.tx_fifo); in ucan_probe()
/openbmc/linux/drivers/spi/
H A Dspi-sh-msiof.c674 void (*tx_fifo)(struct sh_msiof_spi_priv *, in sh_msiof_spi_txrx_once()
702 tx_fifo(p, tx_buf, words, fifo_shift); in sh_msiof_spi_txrx_once()
915 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); in sh_msiof_transfer_one() local
988 tx_fifo = sh_msiof_spi_write_fifo_8; in sh_msiof_transfer_one()
993 tx_fifo = sh_msiof_spi_write_fifo_16u; in sh_msiof_transfer_one()
995 tx_fifo = sh_msiof_spi_write_fifo_16; in sh_msiof_transfer_one()
1004 tx_fifo = sh_msiof_spi_write_fifo_s32u; in sh_msiof_transfer_one()
1006 tx_fifo = sh_msiof_spi_write_fifo_s32; in sh_msiof_transfer_one()
1015 tx_fifo = sh_msiof_spi_write_fifo_32u; in sh_msiof_transfer_one()
1017 tx_fifo = sh_msiof_spi_write_fifo_32; in sh_msiof_transfer_one()
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dtegra_i2c.c153 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
158 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
171 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
266 writel(local, &control->tx_fifo); in send_recv_packets()

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