Searched refs:train (Results 1 – 12 of 12) sorted by relevance
439 void drm_dp_link_train_init(struct drm_dp_link_train *train) in drm_dp_link_train_init() argument441 struct drm_dp_link_train_set *request = &train->request; in drm_dp_link_train_init()442 struct drm_dp_link_train_set *adjust = &train->adjust; in drm_dp_link_train_init()456 train->pattern = DP_TRAINING_PATTERN_DISABLE; in drm_dp_link_train_init()457 train->clock_recovered = false; in drm_dp_link_train_init()458 train->channel_equalized = false; in drm_dp_link_train_init()461 static bool drm_dp_link_train_valid(const struct drm_dp_link_train *train) in drm_dp_link_train_valid() argument463 return train->clock_recovered && train->channel_equalized; in drm_dp_link_train_valid()468 struct drm_dp_link_train_set *request = &link->train.request; in drm_dp_link_apply_training()511 if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE) in drm_dp_link_apply_training()[all …]
159 struct drm_dp_link_train train; member174 void drm_dp_link_train_init(struct drm_dp_link_train *train);
811 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()812 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()813 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()823 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
100 gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) in gt215_link_train_calc() argument138 train->r_100720 = 0; in gt215_link_train_calc()143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()147 train->r_111400 = 0x0; in gt215_link_train_calc()156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train() local178 train->state = NVA3_TRAIN_EXEC; in gt215_link_train()223 ram_wr32(fuc, 0x100720, train->r_100720); in gt215_link_train()224 ram_wr32(fuc, 0x1111e0, train->r_1111e0); in gt215_link_train()225 ram_wr32(fuc, 0x111400, train->r_111400); in gt215_link_train()[all …]
1272 struct gk104_ram_train *train) in gk104_ram_train_type() argument1278 struct nvbios_M0209S *remap = &train->remap; in gk104_ram_train_type()1288 case 0x00: value = &train->type00; break; in gk104_ram_train_type()1289 case 0x01: value = &train->type01; break; in gk104_ram_train_type()1290 case 0x04: value = &train->type04; break; in gk104_ram_train_type()1291 case 0x06: value = &train->type06; break; in gk104_ram_train_type()1292 case 0x07: value = &train->type07; break; in gk104_ram_train_type()1293 case 0x08: value = &train->type08; break; in gk104_ram_train_type()1294 case 0x09: value = &train->type09; break; in gk104_ram_train_type()1327 train->mask |= 1 << M0205E.type; in gk104_ram_train_type()[all …]
2 #Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
655 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph() local657 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) in zynqmp_dp_update_vs_emph()659 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) in zynqmp_dp_update_vs_emph()
20 but the concern is that an attacker can mis-train the CPU BTB to predict
173 An attacker can train the branch predictor to speculatively skip the
537 approached. The two pieces of information are ACK train length and539 `Hybrid Slow Start paper`_. Either ACK train length or packet delay550 How many times the ACK train length threshold is detected554 The sum of CWND detected by ACK train length. Dividing this value by556 ACK train length.
468 the kernel and the company both, and who can help to train others as well.