Searched refs:tisr (Results 1 – 10 of 10) sorted by relevance
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()172 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */ in txx9tmr_interrupt()214 __raw_writel(0, &tmrptr->tisr); in txx9_tmr_init()
201 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index)); in npcm7xx_timer_check_interrupt()216 tc->tisr |= BIT(index); in npcm7xx_timer_reached_zero()326 s->tisr &= ~value; in npcm7xx_timer_write_tisr()459 value = s->tisr; in npcm7xx_timer_read()562 s->tisr = 0x00000000; in npcm7xx_timer_enter_reset()680 VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
16 u32 tisr; member
102 uint32_t tisr; member
23 u32 tisr; /* 0x18 rw */ member
31 unsigned int tisr; /* offset 0x2c */ member
28 u32 tisr; /* 0x28 rw */ member
56 __raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */ in txx9wdt_start()
429 unsigned int tisr; /* offset 0x2c */ member
270 u32 tisr; /* 0x18 rw */ member