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Searched refs:tcsr (Results 1 – 25 of 64) sorted by relevance

123

/openbmc/qemu/hw/timer/
H A Dnpcm7xx_timer.c122 static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) in npcm7xx_tcsr_prescaler() argument
124 return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START, in npcm7xx_tcsr_prescaler()
133 ticks *= npcm7xx_tcsr_prescaler(t->tcsr); in npcm7xx_timer_count_to_ns()
145 npcm7xx_tcsr_prescaler(t->tcsr); in npcm7xx_timer_ns_to_count()
201 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index)); in npcm7xx_timer_check_interrupt()
218 if (t->tcsr & NPCM7XX_TCSR_PERIODIC) { in npcm7xx_timer_reached_zero()
220 if (t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_reached_zero()
224 t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT); in npcm7xx_timer_reached_zero()
241 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_restart()
250 if (t->tcsr & NPCM7XX_TCSR_CEN) { in npcm7xx_timer_read_tdr()
[all …]
H A Drenesas_tmr.c220 FIELD_EX8(tmr->tcsr[ch], TCSR, OSA)); in tmr_read()
222 FIELD_EX8(tmr->tcsr[ch], TCSR, OSB)); in tmr_read()
226 FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE)); in tmr_read()
293 tmr->tcsr[ch] = val; in tmr_write()
417 tmr->tcsr[0] = 0x00; in rtmr_reset()
418 tmr->tcsr[1] = 0x10; in rtmr_reset()
458 VMSTATE_UINT8_ARRAY(tcsr, RTMRState, TMR_CH),
/openbmc/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c114 struct regmap *tcsr; member
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
198 regmap_update_bits(gsbi->tcsr, in gsbi_probe()
201 regmap_update_bits(gsbi->tcsr, in gsbi_probe()
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8660.dtsi150 syscon-tcsr = <&tcsr>;
176 syscon-tcsr = <&tcsr>;
202 syscon-tcsr = <&tcsr>;
237 syscon-tcsr = <&tcsr>;
271 syscon-tcsr = <&tcsr>;
296 syscon-tcsr = <&tcsr>;
645 tcsr: syscon@1a400000 { label
646 compatible = "qcom,tcsr-msm8660", "syscon";
H A Dqcom-ipq8064.dtsi781 syscon-tcsr = <&tcsr>;
820 syscon-tcsr = <&tcsr>;
857 syscon-tcsr = <&tcsr>;
893 syscon-tcsr = <&tcsr>;
936 syscon-tcsr = <&tcsr>;
995 syscon-tcsr = <&tcsr>;
1034 tcsr: syscon@1a400000 { label
1035 compatible = "qcom,tcsr-ipq8064", "syscon";
H A Dqcom-mdm9615.dtsi206 syscon-tcsr = <&tcsr>;
230 syscon-tcsr = <&tcsr>;
371 tcsr: syscon@1a400000 { label
372 compatible = "qcom,tcsr-mdm9615", "syscon";
H A Dqcom-msm8960.dtsi249 syscon-tcsr = <&tcsr>;
346 tcsr: syscon@1a400000 { label
347 compatible = "qcom,tcsr-msm8960", "syscon";
H A Dqcom-sdx65.dtsi314 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
381 compatible = "qcom,tcsr-mutex";
386 tcsr: syscon@1fcb000 { label
387 compatible = "qcom,sdx65-tcsr", "syscon";
H A Dqcom-apq8064.dtsi425 syscon-tcsr = <&tcsr>;
464 syscon-tcsr = <&tcsr>;
625 syscon-tcsr = <&tcsr>;
1163 tcsr: syscon@1a400000 { label
1164 compatible = "qcom,tcsr-apq8064", "syscon";
H A Dqcom-sdx55.dtsi403 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
517 compatible = "qcom,tcsr-mutex";
522 tcsr: syscon@1fc0000 { label
523 compatible = "qcom,sdx55-tcsr", "syscon";
/openbmc/linux/include/clocksource/
H A Dtimer-xilinx.h59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
71 u32 tlr, u32 tcsr);
/openbmc/linux/drivers/pwm/
H A Dpwm-xilinx.c34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, in xilinx_timer_tlr_cycles() argument
39 if (tcsr & TCSR_UDT) in xilinx_timer_tlr_cycles()
45 u32 tlr, u32 tcsr) in xilinx_timer_get_period() argument
49 if (tcsr & TCSR_UDT) in xilinx_timer_get_period()
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_tai.c242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
/openbmc/linux/drivers/pmdomain/qcom/
H A Dcpr.c236 struct regmap *tcsr; member
392 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, in cpr_set_acc() argument
400 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
403 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
413 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
414 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
425 if (drv->tcsr && dir == UP) in cpr_post_voltage()
426 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
1538 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1543 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq5332.dtsi83 qcom,dload-mode = <&tcsr 0x6100>;
194 compatible = "qcom,tcsr-mutex";
199 tcsr: syscon@1937000 { label
200 compatible = "qcom,tcsr-ipq5332", "syscon";
H A Dipq6018.dtsi94 qcom,dload-mode = <&tcsr 0x6100>;
395 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
400 tcsr: syscon@1937000 { label
401 compatible = "qcom,tcsr-ipq6018", "syscon";
722 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
H A Dipq9574.dtsi98 qcom,dload-mode = <&tcsr 0x6100>;
293 compatible = "qcom,tcsr-mutex";
298 tcsr: syscon@1937000 { label
299 compatible = "qcom,tcsr-ipq9574", "syscon";
H A Dipq8074.dtsi116 qcom,dload-mode = <&tcsr 0x6100>;
391 compatible = "qcom,tcsr-mutex";
396 tcsr: syscon@1937000 { label
397 compatible = "qcom,tcsr-ipq8074", "syscon";
H A Dmsm8953.dtsi460 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
782 compatible = "qcom,tcsr-mutex";
787 tcsr: syscon@1937000 { label
788 compatible = "qcom,tcsr-msm8953", "syscon";
793 compatible = "qcom,tcsr-msm8953", "syscon";
1091 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
H A Dmsm8976.dtsi215 qcom,dload-mode = <&tcsr 0x6100>;
796 compatible = "qcom,tcsr-mutex";
801 tcsr: syscon@1937000 { label
802 compatible = "qcom,msm8976-tcsr", "syscon";
H A Dqcs404.dtsi653 * qcom,halt-regs = <&tcsr 0x19004>;
892 compatible = "qcom,tcsr-mutex";
897 tcsr: syscon@1937000 { label
898 compatible = "qcom,qcs404-tcsr", "syscon";
1343 acc-syscon = <&tcsr>;
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c438 struct regmap *tcsr; member
807 if (qphy->tcsr) { in qusb2_phy_init()
808 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1009 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1011 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1013 qphy->tcsr = NULL; in qusb2_phy_probe()
/openbmc/qemu/include/hw/timer/
H A Dnpcm7xx_timer.h66 uint32_t tcsr; member
H A Drenesas_tmr.h49 uint8_t tcsr[TMR_CH]; member
/openbmc/linux/drivers/firmware/
H A Dqcom_scm.c1313 struct device_node *tcsr; in qcom_scm_find_dload_address() local
1319 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); in qcom_scm_find_dload_address()
1320 if (!tcsr) in qcom_scm_find_dload_address()
1323 ret = of_address_to_resource(tcsr, 0, &res); in qcom_scm_find_dload_address()
1324 of_node_put(tcsr); in qcom_scm_find_dload_address()

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