Searched refs:tR (Results 1 – 10 of 10) sorted by relevance
14 unsigned int tR; /* ND_nWE high to ND_nRE low for read */ member
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()458 u32 tR = chip->chip_delay * 1000; in pxa3xx_nand_set_sdr_timing() local463 if (!tR) in pxa3xx_nand_set_sdr_timing()464 tR = 20000; in pxa3xx_nand_set_sdr_timing()473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
181 u16 tR; member
21 read registers (tR). Required if property "gpios" is not used
21 read registers (tR). If not present then a default of 20us is used.
674 timings->tR_max = 1000000ULL * onfi->tR; in onfi_fill_sdr_interface_config()710 timings->tR_max = 1000000ULL * onfi->tR; in onfi_fill_nvddr_interface_config()
458 unsigned int tR; member2446 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()2448 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_interface()2450 if (nfc_tmg.tR + 3 > nfc_tmg.tCH) in marvell_nfc_setup_interface()2451 nfc_tmg.tR = nfc_tmg.tCH - 3; in marvell_nfc_setup_interface()2453 nfc_tmg.tR = 0; in marvell_nfc_setup_interface()2471 NDTR1_TR(nfc_tmg.tR); in marvell_nfc_setup_interface()
318 onfi->tR = le16_to_cpu(p->t_r); in nand_onfi_detect()
1832 tS, tR = self.dmesg[lp]['end'], self.dmesg[phase]['start']1833 tL = tR - tS1836 left = True if tR > tZero else False2022 tS = tR = False2029 if not tR and ps >= self.tResumed:2031 tR = True
977 …efByO+qObUU98vro60zod9ga/9097w3+Ii6sh6+Vm2GtgjVGXlwYNKAWPSZybYZ/V078c9QaDm+tR/+ryQNTOr75CAWCzi7lnr…1105 …efByO+qObUU98vro60zod9ga/9097w3+Ii6sh6+Vm2GtgjVGXlwYNKAWPSZybYZ/V078c9QaDm+tR/+ryQNTOr75CAWCzi7lnr…