1d524dac9SGrant LikelyFreescale Localbus UPM programmed to work with NAND flash 2d524dac9SGrant Likely 3d524dac9SGrant LikelyRequired properties: 4d524dac9SGrant Likely- compatible : "fsl,upm-nand". 5d524dac9SGrant Likely- reg : should specify localbus chip select and size used for the chip. 6d524dac9SGrant Likely- fsl,upm-addr-offset : UPM pattern offset for the address latch. 7d524dac9SGrant Likely- fsl,upm-cmd-offset : UPM pattern offset for the command latch. 8d524dac9SGrant Likely 9d524dac9SGrant LikelyOptional properties: 10d524dac9SGrant Likely- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 11d524dac9SGrant Likely The corresponding address lines are used to select the chip. 12d524dac9SGrant Likely- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins 13d524dac9SGrant Likely (R/B#). For multi-chip devices, "n" GPIO definitions are required 14d524dac9SGrant Likely according to the number of chips. 15*da151e34SBoris Brezillon 16*da151e34SBoris BrezillonDeprecated properties: 17*da151e34SBoris Brezillon- fsl,upm-wait-flags : add chip-dependent short delays after running the 18*da151e34SBoris Brezillon UPM pattern (0x1), after writing a data byte (0x2) or after 19*da151e34SBoris Brezillon writing out a buffer (0x4). 2025985edcSLucas De Marchi- chip-delay : chip dependent delay for transferring data from array to 21d524dac9SGrant Likely read registers (tR). Required if property "gpios" is not used 22d524dac9SGrant Likely (R/B# pins not connected). 23d524dac9SGrant Likely 2483619ea0SJamie LentinEach flash chip described may optionally contain additional sub-nodes 2583619ea0SJamie Lentindescribing partitions of the address space. See partition.txt for more 2683619ea0SJamie Lentindetail. 2783619ea0SJamie Lentin 28d524dac9SGrant LikelyExamples: 29d524dac9SGrant Likely 30d524dac9SGrant Likelyupm@1,0 { 31d524dac9SGrant Likely compatible = "fsl,upm-nand"; 32d524dac9SGrant Likely reg = <1 0 1>; 33d524dac9SGrant Likely fsl,upm-addr-offset = <16>; 34d524dac9SGrant Likely fsl,upm-cmd-offset = <8>; 35d524dac9SGrant Likely gpios = <&qe_pio_e 18 0>; 36d524dac9SGrant Likely 37d524dac9SGrant Likely flash { 38d524dac9SGrant Likely #address-cells = <1>; 39d524dac9SGrant Likely #size-cells = <1>; 40d524dac9SGrant Likely compatible = "..."; 41d524dac9SGrant Likely 42d524dac9SGrant Likely partition@0 { 43d524dac9SGrant Likely ... 44d524dac9SGrant Likely }; 45d524dac9SGrant Likely }; 46d524dac9SGrant Likely}; 47d524dac9SGrant Likely 48d524dac9SGrant Likelyupm@3,0 { 49d524dac9SGrant Likely #address-cells = <0>; 50d524dac9SGrant Likely #size-cells = <0>; 51d524dac9SGrant Likely compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 52d524dac9SGrant Likely reg = <3 0x0 0x800>; 53d524dac9SGrant Likely fsl,upm-addr-offset = <0x10>; 54d524dac9SGrant Likely fsl,upm-cmd-offset = <0x08>; 55d524dac9SGrant Likely /* Multi-chip NAND device */ 56d524dac9SGrant Likely fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 57d524dac9SGrant Likely 58d524dac9SGrant Likely nand@0 { 59d524dac9SGrant Likely #address-cells = <1>; 60d524dac9SGrant Likely #size-cells = <1>; 61d524dac9SGrant Likely 62d524dac9SGrant Likely partition@0 { 63d524dac9SGrant Likely label = "fs"; 64d524dac9SGrant Likely reg = <0x00000000 0x10000000>; 65d524dac9SGrant Likely }; 66d524dac9SGrant Likely }; 67d524dac9SGrant Likely}; 68