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Searched refs:sram_addr_width (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/arm/
H A Darmsse.c84 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
97 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
114 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 18),
587 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); in armsse_sys_config_value()
592 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
603 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
943 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { in armsse_realize()
1161 uint32_t sram_bank_size = 1 << s->sram_addr_width; in armsse_realize()
H A Dmusca.c54 int sram_addr_width; member
380 qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); in musca_init()
620 mmc->sram_addr_width = 15; in musca_a_class_init()
641 mmc->sram_addr_width = 17; in musca_b1_class_init()
H A Dmps2-tz.c127 uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ member
846 qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); in mps2tz_common_init()
1334 mmc->sram_addr_width = 15; in mps2tz_an505_class_init()
1368 mmc->sram_addr_width = 15; in mps2tz_an521_class_init()
1402 mmc->sram_addr_width = 15; in mps3tz_an524_class_init()
1442 mmc->sram_addr_width = 21; in mps3tz_an547_class_init()
/openbmc/qemu/include/hw/arm/
H A Darmsse.h225 uint32_t sram_addr_width; member