| /openbmc/linux/net/sunrpc/auth_gss/ |
| H A D | gss_krb5_wrap.c | 74 int shifted = 0; in _rotate_left() local
78 while (shifted < shift) { in _rotate_left()
79 this_shift = min(shift - shifted, LOCAL_BUF_LEN); in _rotate_left()
81 shifted += this_shift; in _rotate_left()
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| /openbmc/linux/arch/arm/nwfpe/ |
| H A D | softfloat-macros | 35 bits are shifted off, they are ``jammed'' into the least significant bit of
60 bits are shifted off, they are ``jammed'' into the least significant bit of
88 _plus_ the number of bits given in `count'. The shifted result is at most
90 bits shifted off form a second 64-bit result as follows: The _last_ bit
91 shifted off is the most-significant bit of the extra result, and the other
93 bits shifted off were all zero. This extra result is stored in the location
97 value is shifted right by the number of bits given in `count', and the
135 number of bits given in `count'. Any bits shifted off are lost. The value
168 number of bits given in `count'. If any nonzero bits are shifted off, they
212 by 64 _plus_ the number of bits given in `count'. The shifted result is
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/exynos/ |
| H A D | dwmmc.txt | 33 . SelClk_sample: Select sample clock among 8 shifted clocks.
34 . SelClk_drv: Select drv clock among 8 shifted clocks.
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| /openbmc/linux/drivers/media/rc/ |
| H A D | serial_ir.c | 181 unsigned char chunk, shifted; in send_pulse_irdeo() local
190 shifted = chunk << (i * 3); in send_pulse_irdeo()
191 shifted >>= 1; in send_pulse_irdeo()
192 output &= (~shifted); in send_pulse_irdeo()
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-v7.S | 51 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
52 movs r1, r2, lsl r1 @ #1 shifted left by same amount
157 movne r4, r4, lsl r5 @ # of ways shifted into bits [31:...]
158 movne r6, r6, lsl r5 @ 1 shifted left by same amount
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | spi.rst | 9 duplex protocol; for each bit shifted out the MOSI line (one per clock)
10 another is shifted in on the MISO line. Those bits are assembled into
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | epson,rx6110.txt | 28 - spi-cpha: RX6110 works with SPI shifted clock phase
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| /openbmc/qemu/host/include/generic/host/ |
| H A D | store-insert-al16.h.inc | 14 * @val: shifted value to store
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-hid-prodikeys | 26 The octave can be shifted via software up/down 2 octaves.
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| /openbmc/linux/arch/m68k/fpsp040/ |
| H A D | sgetem.S | 109 | shifted bits in d0 and d1
134 | ;be shifted into ms mant
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| /openbmc/qemu/host/include/aarch64/host/ |
| H A D | store-insert-al16.h.inc | 14 * @val: shifted value to store
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | moxtet.txt | 8 - spi-cpha : Required shifted clock phase
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| /openbmc/linux/sound/soc/cirrus/ |
| H A D | Kconfig | 25 state machine and the whole stream can be shifted by one byte
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| /openbmc/linux/Documentation/i2c/ |
| H A D | slave-interface.rst | 113 only means that the previous byte is shifted out to the bus! To ensure seamless
115 still shifted out. If the master sends NACK and stops reading after the byte
116 currently shifted out, this byte requested here is never used. It very likely
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| /openbmc/linux/arch/powerpc/lib/ |
| H A D | div64.S | 39 divwu r11,r11,r9 # then we divide the shifted quantities
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| /openbmc/linux/arch/sh/kernel/ |
| H A D | entry-common.S | 262 * Note: When we're first called, the TRA value must be shifted
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| /openbmc/linux/Documentation/driver-api/media/drivers/ |
| H A D | cx88-devel.rst | 88 Bits are then right shifted into the GP_SAMPLE register at the specified
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| /openbmc/u-boot/doc/device-tree-bindings/serial/ |
| H A D | snps-dw-apb-uart.txt | 23 not present then the register offsets are not shifted.
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| /openbmc/linux/arch/powerpc/boot/ |
| H A D | div64.S | 39 divwu r11,r11,r9 # then we divide the shifted quantities
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| /openbmc/linux/Documentation/input/devices/ |
| H A D | rotary-encoder.rst | 11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
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| /openbmc/qemu/tests/functional/acpi-bits/bits-tests/ |
| H A D | testcpuid.py2 | 58 desc.append("Register values have been shifted by {}".format(shift))
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| /openbmc/linux/arch/parisc/kernel/ |
| H A D | perf_asm.S | 86 ;* is shifted shifted backup immediately. This is to compensate
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-bus.txt | 53 shifted clock phase (CPHA) mode
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| /openbmc/qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 148 /* Match a constant valid for addition (12-bit, optionally shifted). */
175 /* Return true if v16 is a valid 16-bit shifted immediate. */
190 /* Return true if v32 is a valid 32-bit shifted immediate. */
278 /* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
489 /* Add/subtract shifted register instructions (without a shift). */
495 /* Add/subtract shifted register instructions (with a shift). */
527 /* Logical shifted register instructions (without a shift). */
536 /* Logical shifted register instructions (with a shift). */
767 /* This function is for both 3.5.2 (Add/Subtract shifted register), for
776 /* This function is for 3.5.2 (Add/subtract shifted register),
[all …]
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| /openbmc/linux/Documentation/staging/ |
| H A D | crc32.rst | 53 Notice how, to get at bit 32 of the shifted remainder, we look
167 in parallel. Each step, the 32-bit CRC is shifted 64 bits and XORed
|