| /openbmc/u-boot/board/engicam/common/ |
| H A D | spl.c | 245 .rst_to_cke = 0x23,
277 .rst_to_cke = 0x23,
294 .rst_to_cke = 0x23,
344 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/liebherr/mccmon6/ |
| H A D | spl.c | 186 .rst_to_cke = 0x23,
227 .rst_to_cke = 0x23,
244 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/wandboard/ |
| H A D | spl.c | 235 .rst_to_cke = 0x23,
278 .rst_to_cke = 0x23,
297 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/compulab/cm_fx6/ |
| H A D | spl.c | 105 .rst_to_cke = 0x23,
172 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/bachmann/ot1200/ |
| H A D | ot1200_spl.c | 84 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/ccv/xpress/ |
| H A D | spl.c | 60 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/barco/platinum/ |
| H A D | spl_picon.c | 136 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| H A D | spl_titanium.c | 139 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| /openbmc/u-boot/board/phytec/pcl063/ |
| H A D | spl.c | 65 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | spl.c | 229 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
234 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
|
| /openbmc/u-boot/board/bticino/mamoj/ |
| H A D | spl.c | 124 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 128 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| H A D | opos6ul.c | 193 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/technexion/pico-imx6ul/ |
| H A D | spl.c | 71 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/dhelectronics/dh_imx6/ |
| H A D | dh_imx6_spl.c | 251 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
270 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 637 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
677 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/udoo/ |
| H A D | udoo_spl.c | 192 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/liebherr/display5/ |
| H A D | spl.c | 180 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| /openbmc/u-boot/board/k+p/kp_imx6q_tpc/ |
| H A D | kp_imx6q_tpc_spl.c | 243 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| /openbmc/u-boot/board/sks-kinkel/sksimx6/ |
| H A D | sksimx6.c | 333 .rst_to_cke = 0x23,
|
| /openbmc/u-boot/board/freescale/mx6slevk/ |
| H A D | mx6slevk.c | 412 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ in spl_dram_init()
|
| /openbmc/u-boot/board/phytec/pcm058/ |
| H A D | pcm058.c | 506 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | gw_ventana_spl.c | 507 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|
| /openbmc/u-boot/board/kosagi/novena/ |
| H A D | novena_spl.c | 519 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
| /openbmc/u-boot/board/freescale/mx6sxsabresd/ |
| H A D | mx6sxsabresd.c | 522 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
|