| /openbmc/qemu/target/arm/ |
| H A D | cortex-regs.c | 40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | helper.c | 68 return ri->resetvalue; in read_raw_cp_reg()
637 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
642 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
657 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
663 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
674 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
719 .resetvalue = 0 },
722 .resetvalue = 0 },
726 .resetvalue = 0 },
734 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | debug_helper.c | 950 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
954 .type = ARM_CP_CONST, .resetvalue = 0 },
957 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
965 .resetvalue = 0 },
973 .type = ARM_CP_CONST, .resetvalue = 0 },
983 .type = ARM_CP_CONST, .resetvalue = 0 },
987 .type = ARM_CP_CONST, .resetvalue = 0 },
992 .type = ARM_CP_CONST, .resetvalue = 0 },
1002 .type = ARM_CP_CONST, .resetvalue = 0 },
1021 .access = PL1_R, .resetvalue = 10,
[all …]
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| H A D | cpregs.h | 895 uint64_t resetvalue; member
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| H A D | cpu.c | 208 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
210 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | cpu64.c | 482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
487 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
490 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
493 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
496 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
515 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
[all …]
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| H A D | cpu32.c | 200 .resetvalue = 0 in arm1026_initfn()
338 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
340 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 .access = PL1_RW, .resetvalue = 0,
392 .access = PL1_RW, .resetvalue = 0,
395 .access = PL1_RW, .resetvalue = 0,
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
[all …]
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| H A D | translate.c | 3114 tmp64 = tcg_constant_i64(ri->resetvalue); in do_coproc_insn()
3134 tmp = tcg_constant_i32(ri->resetvalue); in do_coproc_insn()
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| H A D | translate-a64.c | 2547 tcg_gen_movi_i64(tcg_rt, ri->resetvalue); in handle_sys()
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| /openbmc/u-boot/arch/nios2/dts/ |
| H A D | 3c120_devboard.dts | 145 resetvalue = <255>;
159 resetvalue = <0>;
173 resetvalue = <0>;
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| H A D | 10m50_devboard.dts | 200 resetvalue = <15>;
224 resetvalue = <0>;
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | altera_pio.txt | 19 resetvalue = <255>;
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 2585 .resetvalue = 0x7,
2611 .resetvalue = 0xf,
2627 .resetvalue = 0xf,
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| /openbmc/qemu/target/arm/hvf/ |
| H A D | hvf.c | 1252 *val = ri->resetvalue; in hvf_sysreg_read_cp()
|