| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_link_enc_cfg.c | 71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT) in get_assignment()
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i]; in get_assignment()
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_assignment()
88 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_stream_using_link_enc()
114 struct link_enc_assignment assignment = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in remove_link_enc_assignment()
117 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; in remove_link_enc_assignment()
122 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = eng_id; in remove_link_enc_assignment()
125 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id = ENGINE_ID_UNKNOWN; in remove_link_enc_assignment()
126 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream = NULL; in remove_link_enc_assignment()
150 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i] = (struct link_enc_assignment){ in add_link_enc_assignment()
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| H A D | dc_resource.c | 471 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
478 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
481 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
485 struct resource_context *res_ctx, in resource_reference_clock_source() argument
492 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
495 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
499 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
506 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
509 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
646 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| H A D | dc_stream.c | 256 struct resource_context *res_ctx; in program_cursor_attributes() local
262 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
265 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes()
401 struct resource_context *res_ctx; in program_cursor_position() local
407 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
410 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position()
579 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
580 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
583 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
585 if (res_ctx->pipe_ctx[i].stream != stream || !tg) in dc_stream_get_vblank_counter()
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| H A D | dc.c | 417 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
452 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
483 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
543 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_crc_window()
594 &dc->current_state->res_ctx, stream); in dc_stream_configure_crc()
660 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
684 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_set_dyn_expansion()
686 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dyn_expansion()
706 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
708 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dither_option()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource_helpers.c | 129 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
147 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
174 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
191 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
216 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_any_surfaces_rotated()
311 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] && in dcn32_determine_det_override()
319 current_plane = context->res_ctx.pipe_ctx[j].plane_state; in dcn32_determine_det_override()
321 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && in dcn32_determine_det_override()
322 context->res_ctx.pipe_ctx[k].plane_state == current_plane) { in dcn32_determine_det_override()
330 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && in dcn32_determine_det_override()
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| H A D | dcn32_resource.c | 1590 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1602 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1605 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
1612 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1622 res_ctx->is_mpc_3dlut_acquired[i] = false; in dcn32_release_post_bldn_3dlut()
1640 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1683 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1712 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_retain_phantom_pipes()
1735 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_remove_phantom_pipes()
1797 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
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| H A D | dcn32_hwseq.c | 229 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
348 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config()
379 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
399 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
609 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_force_pstate()
630 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_force_pstate()
661 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_mall_sel()
721 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_program_mall_pipe_config()
1133 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; in dcn32_update_odm()
1208 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_resync_fifo_dccg_dio()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | resource.h | 115 struct resource_context *res_ctx,
120 struct resource_context *res_ctx,
125 struct resource_context *res_ctx,
138 struct resource_context *res_ctx,
142 struct resource_context *res_ctx,
332 struct resource_context *res_ctx,
360 struct resource_context *res_ctx,
403 struct resource_context *res_ctx,
419 const struct resource_context *res_ctx,
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| H A D | core_types.h | 152 struct resource_context *res_ctx,
157 struct resource_context *res_ctx,
169 struct resource_context *res_ctx,
176 struct resource_context *res_ctx,
510 struct resource_context res_ctx; member
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 988 struct resource_context *res_ctx, in dcn20_populate_dml_writeback_from_context() argument
996 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
998 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
1040 …wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / … in dcn20_fpu_set_wb_arb_params()
1047 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
1049 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
1062 if (context->res_ctx.pipe_ctx[i].plane_state) in decide_zstate_support()
1174 if (!context->res_ctx.pipe_ctx[i].stream) in dcn20_calculate_dlg_params()
1176 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_calculate_dlg_params()
1183 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { in dcn20_calculate_dlg_params()
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| H A D | dcn20_fpu.h | 32 struct resource_context *res_ctx,
88 struct resource_context *res_ctx,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1297 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1310 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1316 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1324 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1329 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { in dcn20_acquire_dsc()
1331 res_ctx->is_dsc_acquired[dsc_old->inst] = true; in dcn20_acquire_dsc()
1337 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1339 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1344 void dcn20_release_dsc(struct resource_context *res_ctx, in dcn20_release_dsc() argument
1352 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
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| H A D | dcn20_resource.h | 130 void dcn20_release_dsc(struct resource_context *res_ctx,
135 struct resource_context *res_ctx,
141 struct resource_context *res_ctx,
145 struct resource_context *res_ctx,
149 struct resource_context *res_ctx,
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| H A D | dcn20_hwseq.c | 1811 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1812 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1820 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1832 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) in dcn20_program_front_end_for_ctx()
1834 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_program_front_end_for_ctx()
1847 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], in dcn20_program_front_end_for_ctx()
1848 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
1854 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; in dcn20_program_front_end_for_ctx()
1856 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && in dcn20_program_front_end_for_ctx()
1857 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { in dcn20_program_front_end_for_ctx()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 147 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_replay_copy_settings() local
151 if (res_ctx && in dmub_replay_copy_settings()
152 res_ctx->pipe_ctx[i].stream && in dmub_replay_copy_settings()
153 res_ctx->pipe_ctx[i].stream->link && in dmub_replay_copy_settings()
154 res_ctx->pipe_ctx[i].stream->link == link && in dmub_replay_copy_settings()
155 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_replay_copy_settings()
156 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_replay_copy_settings()
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| H A D | dmub_psr.c | 304 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
308 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
309 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
310 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
311 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 330 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_helper_populate_phantom_dlg_params()
559 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_set_phantom_stream_timing()
636 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_get_num_free_pipes()
681 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
713 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
756 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_enough_pipes_for_subvp()
806 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in subvp_subvp_schedulable()
885 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
900 drr_pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
982 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_vblank_schedulable()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.h | 76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
84 struct resource_context *res_ctx,
91 struct resource_context *res_ctx,
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| H A D | dcn30_resource.c | 1323 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1330 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1341 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1344 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1386 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1390 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1407 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1430 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1445 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
1449 res_ctx->is_mpc_3dlut_acquired[i] = true; in dcn30_acquire_post_bldn_3dlut()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce60_apply_ctx_for_surface()
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| /openbmc/linux/lib/kunit/ |
| H A D | resource.c | 131 struct kunit_action_ctx *res_ctx = container_of(res, struct kunit_action_ctx, res); in __kunit_action_match() local
138 return (match_ctx->func == res_ctx->func) && (match_ctx->ctx == res_ctx->ctx); in __kunit_action_match()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.c | 1096 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1418 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1684 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1686 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
1843 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
1872 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
1884 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
1887 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
1888 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
1896 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( in dce110_set_safe_displaymarks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/ |
| H A D | dcn315_resource.c | 1633 struct resource_context *res_ctx = &context->res_ctx; in allow_pixel_rate_crb() local
1640 if (!res_ctx->pipe_ctx[i].stream) in allow_pixel_rate_crb()
1644 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || in allow_pixel_rate_crb()
1645 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || in allow_pixel_rate_crb()
1646 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width in allow_pixel_rate_crb()
1647 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || in allow_pixel_rate_crb()
1648 res_ctx->pipe_ctx[i].plane_state->src_rect.height in allow_pixel_rate_crb()
1649 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) in allow_pixel_rate_crb()
1652 …if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_c… in allow_pixel_rate_crb()
1664 struct resource_context *res_ctx = &context->res_ctx; in dcn315_populate_dml_pipes_from_context() local
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| H A D | dce100_hw_sequencer.c | 112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 312 struct resource_context *res_ctx = &context->res_ctx; in dcn314_populate_dml_pipes_from_context_fpu() local
326 if (!res_ctx->pipe_ctx[i].stream) in dcn314_populate_dml_pipes_from_context_fpu()
328 pipe = &res_ctx->pipe_ctx[i]; in dcn314_populate_dml_pipes_from_context_fpu()
413 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn314_populate_dml_pipes_from_context_fpu()
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