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Searched refs:regs_wo (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/net/
H A Dcadence_gem.h69 uint32_t regs_wo[CADENCE_GEM_MAXREG]; member
/openbmc/qemu/hw/net/
H A Dcadence_gem.c626 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); in gem_init_register_masks()
627 s->regs_wo[R_NWCTRL] = 0x00073E60; in gem_init_register_masks()
628 s->regs_wo[R_IER] = 0x07FFFFFF; in gem_init_register_masks()
629 s->regs_wo[R_IDR] = 0x07FFFFFF; in gem_init_register_masks()
631 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; in gem_init_register_masks()
632 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; in gem_init_register_masks()
1582 retval &= ~(s->regs_wo[offset]); in gem_read()