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Searched refs:regs_ro (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/net/
H A Dcadence_gem.c595 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); in gem_init_register_masks()
596 s->regs_ro[R_NWCTRL] = 0xFFF80000; in gem_init_register_masks()
597 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; in gem_init_register_masks()
598 s->regs_ro[R_DMACFG] = 0x8E00F000; in gem_init_register_masks()
599 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; in gem_init_register_masks()
600 s->regs_ro[R_RXQBASE] = 0x00000003; in gem_init_register_masks()
601 s->regs_ro[R_TXQBASE] = 0x00000003; in gem_init_register_masks()
602 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; in gem_init_register_masks()
603 s->regs_ro[R_ISR] = 0xFFFFFFFF; in gem_init_register_masks()
604 s->regs_ro[R_IMR] = 0xFFFFFFFF; in gem_init_register_masks()
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c1705 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~s->cq_mask); in riscv_iommu_process_cq_control()
1713 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~0); in riscv_iommu_process_cq_control()
1736 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask); in riscv_iommu_process_fq_control()
1743 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~0); in riscv_iommu_process_fq_control()
1766 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQH], ~s->pq_mask); in riscv_iommu_process_pq_control()
1773 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQH], ~0); in riscv_iommu_process_pq_control()
1915 uint64_t ro = ldn_le_p(&s->regs_ro[reg_addr], size); in riscv_iommu_write_reg_val()
2152 s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); in riscv_iommu_realize()
2156 memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE); in riscv_iommu_realize()
2169 stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL], in riscv_iommu_realize()
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H A Driscv-iommu.h80 uint8_t *regs_ro; /* read-only mask */ member
/openbmc/qemu/include/hw/net/
H A Dcadence_gem.h71 uint32_t regs_ro[CADENCE_GEM_MAXREG]; member