/openbmc/linux/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_mtl.c | 23 u32 reg_val; in sxgbe_mtl_init() local 25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init() 26 reg_val &= ETS_RST; in sxgbe_mtl_init() 31 reg_val &= ETS_WRR; in sxgbe_mtl_init() 34 reg_val |= ETS_WFQ; in sxgbe_mtl_init() 37 reg_val |= ETS_DWRR; in sxgbe_mtl_init() 40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init() 44 reg_val &= RAA_SP; in sxgbe_mtl_init() 47 reg_val |= RAA_WSP; in sxgbe_mtl_init() 50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init() [all …]
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/openbmc/linux/drivers/input/keyboard/ |
H A D | imx_keypad.c | 83 unsigned short reg_val; in imx_keypad_scan_matrix() local 94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix() 95 reg_val |= 0xff00; in imx_keypad_scan_matrix() 96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix() 98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix() 99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix() 100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix() 104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix() 105 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix() 106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix() [all …]
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/openbmc/u-boot/drivers/mtd/nand/raw/ |
H A D | arasan_nfc.c | 266 u32 reg_val; in arasan_nand_select_chip() local 268 reg_val = readl(&arasan_nand_base->memadr_reg2); in arasan_nand_select_chip() 270 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; in arasan_nand_select_chip() 271 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip() 273 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; in arasan_nand_select_chip() 274 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip() 280 u32 reg_val; in arasan_nand_enable_ecc() local 282 reg_val = readl(&arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc() 283 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; in arasan_nand_enable_ecc() 285 writel(reg_val, &arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc() [all …]
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H A D | tegra_nand.c | 117 u32 reg_val; in nand_waitfor_cmd_completion() local 128 reg_val = readl(®->dma_mst_ctrl); in nand_waitfor_cmd_completion() 136 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion() 138 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion() 207 int reg_val; in nand_dev_ready() local 212 reg_val = readl(&info->reg->status); in nand_dev_ready() 213 if (reg_val & STATUS_RBSY0) in nand_dev_ready() 239 u32 reg_val; in nand_clear_interrupt_status() local 242 reg_val = readl(®->isr); in nand_clear_interrupt_status() 243 writel(reg_val, ®->isr); in nand_clear_interrupt_status() [all …]
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/openbmc/u-boot/drivers/video/tegra124/ |
H A D | sor.c | 62 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local 63 reg_val &= ~mask; in tegra_sor_write_field() 64 reg_val |= val; in tegra_sor_write_field() 65 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field() 93 u32 reg_val = 0; in tegra_dc_sor_poll_register() local 98 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register() 99 if (((reg_val & mask) == exp_val)) in tegra_dc_sor_poll_register() 105 reg, reg_val, mask, exp_val); in tegra_dc_sor_poll_register() 113 u32 reg_val; in tegra_dc_sor_set_power_state() local 118 reg_val = pu_pd ? PWR_NORMAL_STATE_PU : in tegra_dc_sor_set_power_state() [all …]
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/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/ |
H A D | octep_cn9k_pf.c | 266 u64 reg_val; in octep_setup_iq_regs_cn93_pf() local 269 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf() 272 if (!(reg_val & CN93_R_IN_CTL_IDLE)) { in octep_setup_iq_regs_cn93_pf() 274 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf() 275 } while (!(reg_val & CN93_R_IN_CTL_IDLE)); in octep_setup_iq_regs_cn93_pf() 278 reg_val |= CN93_R_IN_CTL_RDSIZE; in octep_setup_iq_regs_cn93_pf() 279 reg_val |= CN93_R_IN_CTL_IS_64B; in octep_setup_iq_regs_cn93_pf() 280 reg_val |= CN93_R_IN_CTL_ESR; in octep_setup_iq_regs_cn93_pf() 281 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val); in octep_setup_iq_regs_cn93_pf() 304 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; in octep_setup_iq_regs_cn93_pf() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_helper.c | 146 uint32_t reg_val) in dmub_reg_value_burst_set_pack() argument 164 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack() 229 uint32_t reg_val; in generic_reg_update_ex() local 245 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex() 246 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex() 247 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex() 248 return reg_val; in generic_reg_update_ex() 252 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex() argument 268 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_set_ex() 272 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); in generic_reg_set_ex() [all …]
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/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | af9033_priv.h | 19 struct reg_val { struct 87 static const struct reg_val ofsm_init[] = { 202 static const struct reg_val tuner_init_tua9001[] = { 246 static const struct reg_val tuner_init_fc0011[] = { 309 static const struct reg_val tuner_init_fc0012[] = { 354 static const struct reg_val tuner_init_mxl5007t[] = { 391 static const struct reg_val tuner_init_tda18218[] = { 427 static const struct reg_val tuner_init_fc2580[] = { 467 static const struct reg_val ofsm_init_it9135_v1[] = { 582 static const struct reg_val tuner_init_it9135_38[] = { [all …]
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/openbmc/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 66 u32 reg_val; in mctl_ddr3_reset() local 69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset() 71 if ((reg_val & CPU_CFG_CHIP_VER_MASK) != in mctl_ddr3_reset() 239 u32 reg_val; in mctl_setup_dram_clock() local 246 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock() 247 reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ in mctl_setup_dram_clock() 248 reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ in mctl_setup_dram_clock() 249 reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ in mctl_setup_dram_clock() 250 reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ in mctl_setup_dram_clock() 253 reg_val |= CCM_PLL5_CTRL_P(1); in mctl_setup_dram_clock() [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-mt65xx.c | 271 u32 reg_val; in mtk_spi_reset() local 274 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset() 275 reg_val |= SPI_CMD_RST; in mtk_spi_reset() 276 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset() 278 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset() 279 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset() 280 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset() 290 u32 reg_val; in mtk_spi_set_hw_cs_timing() local 309 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing() 313 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing() [all …]
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H A D | spi-slave-mt27xx.c | 100 u32 reg_val; in mtk_spi_slave_disable_dma() local 102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma() 103 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma() 104 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma() 105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma() 110 u32 reg_val; in mtk_spi_slave_disable_xfer() local 112 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer() 113 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer() 114 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer() 115 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer() [all …]
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_vbif.c | 61 u32 reg_val; in dpu_hw_set_mem_type() local 79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type() 80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type() 81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type() 82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type() 89 u32 reg_val; in dpu_hw_set_limit_conf() local 100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf() 101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf() 102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf() 103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf() [all …]
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/openbmc/u-boot/arch/arm/mach-imx/mx7/ |
H A D | ddr.c | 114 u32 reg_val, field_val; in imx_ddr_size() local 118 reg_val = readl(&ddrc_regs->mstr); in imx_ddr_size() 119 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT; in imx_ddr_size() 122 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT; in imx_ddr_size() 127 reg_val = readl(&ddrc_regs->addrmap2); in imx_ddr_size() 128 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT; in imx_ddr_size() 131 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT; in imx_ddr_size() 134 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT; in imx_ddr_size() 137 field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT; in imx_ddr_size() 140 reg_val = readl(&ddrc_regs->addrmap3); in imx_ddr_size() [all …]
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/openbmc/u-boot/drivers/usb/musb-new/ |
H A D | sunxi.c | 97 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) in USBC_WakeUp_ClearChangeDetect() argument 99 u32 temp = reg_val; in USBC_WakeUp_ClearChangeDetect() 110 u32 reg_val; in USBC_EnableIdPullUp() local 112 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableIdPullUp() 113 reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN); in USBC_EnableIdPullUp() 114 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); in USBC_EnableIdPullUp() 115 musb_writel(base, USBC_REG_o_ISCR, reg_val); in USBC_EnableIdPullUp() 120 u32 reg_val; in USBC_EnableDpDmPullUp() local 122 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableDpDmPullUp() 123 reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN); in USBC_EnableDpDmPullUp() [all …]
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/openbmc/linux/drivers/net/ethernet/allwinner/ |
H A D | sun4i-emac.c | 105 unsigned int reg_val; in emac_update_speed() local 108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed() 109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed() 111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed() 112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed() 118 unsigned int reg_val; in emac_update_duplex() local 121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex() 122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex() 124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex() 125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex() [all …]
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/openbmc/linux/arch/riscv/kvm/ |
H A D | vcpu_onereg.c | 127 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local 134 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config() 139 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config() 144 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config() 147 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config() 150 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config() 153 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config() 156 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config() 162 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config() 176 unsigned long i, isa_ext, reg_val; in kvm_riscv_vcpu_set_reg_config() local [all …]
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/openbmc/linux/sound/drivers/opl3/ |
H A D | opl3_synth.c | 396 unsigned char reg_val; in snd_opl3_play_note() local 416 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note() 418 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note() 420 reg_val = 0x00; in snd_opl3_play_note() 423 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note() 425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note() 427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note() 431 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note() 444 unsigned char reg_val; in snd_opl3_set_voice() local 470 reg_val = 0x00; in snd_opl3_set_voice() [all …]
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/openbmc/linux/drivers/gpu/drm/msm/hdmi/ |
H A D | hdmi_hdcp.c | 45 u32 reg_val; member 199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local 203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq() 204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq() 210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq() 213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq() 214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq() 228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq() 230 __func__, reg_val); in msm_hdmi_hdcp_irq() 284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local [all …]
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/openbmc/linux/arch/arm/mach-qcom/ |
H A D | platsmp.c | 84 u32 reg_val; in cortex_a7_release_secondary() local 103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary() 104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary() 111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary() 112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary() 113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary() 114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary() 117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary() 118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary() 122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary() [all …]
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/openbmc/linux/arch/powerpc/platforms/powernv/ |
H A D | opal-fadump.h | 83 __be64 reg_val; member 88 u64 reg_val) in opal_fadump_set_regval_regnum() argument 92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum() 98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum() 101 regs->link = reg_val; in opal_fadump_set_regval_regnum() 104 regs->xer = reg_val; in opal_fadump_set_regval_regnum() 107 regs->dar = reg_val; in opal_fadump_set_regval_regnum() 110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum() 113 regs->nip = reg_val; in opal_fadump_set_regval_regnum() 116 regs->msr = reg_val; in opal_fadump_set_regval_regnum() [all …]
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/openbmc/linux/arch/mips/pci/ |
H A D | fixup-malta.c | 70 unsigned char reg_val; in malta_piix_func0_fixup() local 84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); in malta_piix_func0_fixup() 85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup() 88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup() 98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); in malta_piix_func0_fixup() 99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup() 109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val); in malta_piix_func0_fixup() 110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup() 111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup() 124 unsigned char reg_val; in malta_piix_func1_fixup() local [all …]
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/openbmc/u-boot/drivers/net/phy/ |
H A D | mscc.c | 287 u16 reg_val; in vsc8584_cmd() local 297 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd() 300 (reg_val & PROC_CMD_NCOMPLETED) && in vsc8584_cmd() 301 !(reg_val & PROC_CMD_FAILED)); in vsc8584_cmd() 306 if (reg_val & PROC_CMD_FAILED) in vsc8584_cmd() 308 if (reg_val & PROC_CMD_NCOMPLETED) in vsc8584_cmd() 1010 u16 reg_val; in mscc_vsc8531_vsc8541_init_scripts() local 1020 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts() 1021 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, in mscc_vsc8531_vsc8541_init_scripts() 1025 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts() [all …]
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/openbmc/linux/drivers/hwmon/ |
H A D | ltc2992.c | 410 int reg_val; in ltc2992_get_voltage() local 412 reg_val = ltc2992_read_reg(st, reg, 2); in ltc2992_get_voltage() 413 if (reg_val < 0) in ltc2992_get_voltage() 414 return reg_val; in ltc2992_get_voltage() 416 reg_val = reg_val >> 4; in ltc2992_get_voltage() 417 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000); in ltc2992_get_voltage() 432 int reg_val; in ltc2992_read_gpio_alarm() local 440 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1); in ltc2992_read_gpio_alarm() 441 if (reg_val < 0) in ltc2992_read_gpio_alarm() 442 return reg_val; in ltc2992_read_gpio_alarm() [all …]
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/openbmc/linux/drivers/ata/ |
H A D | ahci_sunxi.c | 55 u32 reg_val; in sunxi_clrbits() local 57 reg_val = readl(reg); in sunxi_clrbits() 58 reg_val &= ~(clr_val); in sunxi_clrbits() 59 writel(reg_val, reg); in sunxi_clrbits() 64 u32 reg_val; in sunxi_setbits() local 66 reg_val = readl(reg); in sunxi_setbits() 67 reg_val |= set_val; in sunxi_setbits() 68 writel(reg_val, reg); in sunxi_setbits() 73 u32 reg_val; in sunxi_clrsetbits() local 75 reg_val = readl(reg); in sunxi_clrsetbits() [all …]
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/openbmc/linux/drivers/net/ethernet/cavium/liquidio/ |
H A D | cn23xx_vf_device.c | 68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local 70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues() 71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues() 73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues() 83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues() 86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues() 88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues() 90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues() 153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local 160 reg_val = in cn23xx_vf_setup_global_output_regs() [all …]
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