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Searched refs:reg_state (Results 1 – 25 of 77) sorted by relevance

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/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c211 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) in ras_init_common() argument
217 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); in ras_init_common()
220 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); in ras_init_common()
222 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); in ras_init_common()
224 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); in ras_init_common()
226 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); in ras_init_common()
229 stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); in ras_init_common()
232 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, in hdm_init_common() argument
239 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, in hdm_init_common()
241 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); in hdm_init_common()
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H A Dcxl-device-utils.c110 static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, in mailbox_mem_writel() argument
126 reg_state[offset / sizeof(*reg_state)] = value; in mailbox_mem_writel()
129 static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset, in mailbox_mem_writeq() argument
148 reg_state[offset / sizeof(*reg_state)] = value; in mailbox_mem_writeq()
/openbmc/qemu/tests/tcg/i386/
H A Dtest-mmx.c28 } reg_state; typedef
34 reg_state *init;
37 reg_state initI;
38 reg_state initF32;
39 reg_state initF64;
64 static void dump_regs(reg_state *s, int ff) in dump_regs()
76 static void compare_state(const reg_state *a, const reg_state *b) in compare_state()
145 reg_state result; in run_test()
146 reg_state *init = t->init; in run_test()
266 static void init_all(reg_state *s) in init_all()
H A Dtest-avx.c21 } reg_state; typedef
27 reg_state *init;
30 reg_state initI;
31 reg_state initF16;
32 reg_state initF32;
33 reg_state initF64;
52 static void dump_regs(reg_state *s) in dump_regs()
64 static void compare_state(const reg_state *a, const reg_state *b) in compare_state()
141 reg_state result; in run_test()
142 reg_state *init = t->init; in run_test()
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc_reg.h33 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ argument
34 u32 *reg_state__ = (reg_state); \
40 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ argument
41 u32 *reg_state__ = (reg_state); \
/openbmc/linux/drivers/infiniband/ulp/ipoib/
H A Dipoib_vlan.c113 WARN_ON(ppriv->dev->reg_state != NETREG_REGISTERED); in __ipoib_vlan_add()
180 if (pdev->reg_state != NETREG_REGISTERED) { in ipoib_vlan_add()
205 if (result && ndev->reg_state == NETREG_UNINITIALIZED) in ipoib_vlan_add()
238 if (dev->reg_state == NETREG_REGISTERED) { in ipoib_vlan_delete_task()
262 if (pdev->reg_state != NETREG_REGISTERED) { in ipoib_vlan_delete()
/openbmc/linux/net/core/
H A Dxdp.c137 if (xdp_rxq->reg_state != REG_STATE_REGISTERED) { in xdp_rxq_info_unreg_mem_model()
149 if (xdp_rxq->reg_state == REG_STATE_UNUSED) in xdp_rxq_info_unreg()
154 xdp_rxq->reg_state = REG_STATE_UNREGISTERED; in xdp_rxq_info_unreg()
174 if (xdp_rxq->reg_state == REG_STATE_UNUSED) { in __xdp_rxq_info_reg()
179 if (xdp_rxq->reg_state == REG_STATE_REGISTERED) { in __xdp_rxq_info_reg()
191 xdp_rxq->reg_state = REG_STATE_REGISTERED; in __xdp_rxq_info_reg()
198 xdp_rxq->reg_state = REG_STATE_UNUSED; in xdp_rxq_info_unused()
204 return (xdp_rxq->reg_state == REG_STATE_REGISTERED); in xdp_rxq_info_is_reg()
351 if (xdp_rxq->reg_state != REG_STATE_REGISTERED) { in xdp_rxq_info_reg_mem_model()
780 if (dev->reg_state == NETREG_REGISTERED) in xdp_set_features_flag()
H A Dlink_watch.c51 if (dev->reg_state <= NETREG_REGISTERED) in default_operstate()
H A Ddev.c2934 if (dev->reg_state == NETREG_REGISTERED || in netif_set_real_num_tx_queues()
2935 dev->reg_state == NETREG_UNREGISTERING) { in netif_set_real_num_tx_queues()
2983 if (dev->reg_state == NETREG_REGISTERED) { in netif_set_real_num_rx_queues()
5869 if (skb->dev->reg_state == NETREG_UNREGISTERING) { in flush_backlog()
5878 if (skb->dev->reg_state == NETREG_UNREGISTERING) { in flush_backlog()
10139 BUG_ON(dev->reg_state != NETREG_UNINITIALIZED); in register_netdevice()
10235 dev->reg_state = ret ? NETREG_UNREGISTERED : NETREG_REGISTERED; in register_netdevice()
10324 dev->reg_state = NETREG_DUMMY; in init_dummy_netdev()
10521 if (unlikely(dev->reg_state != NETREG_UNREGISTERING)) { in netdev_run_todo()
10528 dev->reg_state = NETREG_UNREGISTERED; in netdev_run_todo()
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/openbmc/qemu/hw/pci-bridge/
H A Dpci_expander_bridge.c301 uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers; in pxb_cxl_dev_reset() local
305 cxl_component_register_init_common(reg_state, write_msk, CXL2_RC); in pxb_cxl_dev_reset()
317 ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0); in pxb_cxl_dev_reset()
319 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, in pxb_cxl_dev_reset()
H A Dcxl_upstream.c89 uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
92 cxl_component_register_init_common(reg_state, write_msk, in latch_registers()
94 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); in latch_registers()
H A Dcxl_downstream.c38 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
41 cxl_component_register_init_common(reg_state, write_msk, in latch_registers()
H A Dcxl_root_port.c101 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
104 cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT); in latch_registers()
/openbmc/qemu/hw/mem/
H A Dcxl_type3.c1200 uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; in ct3d_reset() local
1204 cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE); in ct3d_reset()
1416 uint32_t *reg_state; in qmp_cxl_inject_uncorrectable_errors() local
1437 reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; in qmp_cxl_inject_uncorrectable_errors()
1451 ~ldl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK))) { in qmp_cxl_inject_uncorrectable_errors()
1496 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, unc_err); in qmp_cxl_inject_uncorrectable_errors()
1508 uint32_t *reg_state; in qmp_cxl_inject_correctable_error() local
1526 reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; in qmp_cxl_inject_correctable_error()
1527 cor_err = ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS); in qmp_cxl_inject_correctable_error()
1536 ~ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK))) { in qmp_cxl_inject_correctable_error()
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/openbmc/linux/drivers/infiniband/core/
H A Droce_gid_mgmt.c344 if (ndev->reg_state >= NETREG_UNREGISTERING) in enum_netdev_ipv4_ips()
389 if (ndev->reg_state >= NETREG_UNREGISTERING) in enum_netdev_ipv6_ips()
769 if (ndev->reg_state < NETREG_UNREGISTERED) in netdevice_event()
777 if (ndev->reg_state == NETREG_REGISTERED) { in netdevice_event()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dscheduler.c85 u32 *reg_state, bool save) in sr_oa_regs() argument
105 workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; in sr_oa_regs()
110 workload->flex_mmio[i] = reg_state[state_offset + 1]; in sr_oa_regs()
113 reg_state[ctx_oactxctrl] = in sr_oa_regs()
115 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; in sr_oa_regs()
121 reg_state[state_offset] = mmio; in sr_oa_regs()
122 reg_state[state_offset + 1] = workload->flex_mmio[i]; in sr_oa_regs()
H A Dmmio_context.c464 const u32 *reg_state = ce->lrc_reg_state; in is_inhibit_context() local
469 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); in is_inhibit_context()
/openbmc/linux/net/phonet/
H A Dpn_dev.c120 if ((dev->reg_state == NETREG_REGISTERED) && in phonet_device_get()
215 if ((pnd->netdev->reg_state != NETREG_REGISTERED) || in phonet_address_lookup()
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dipoib_tx.c94 if (unlikely(dev->reg_state != NETREG_REGISTERED)) in hfi1_ipoib_check_queue_stopped()
624 if (likely(txq->priv->netdev->reg_state == NETREG_REGISTERED)) { in hfi1_ipoib_sdma_sleep()
664 if (likely(txq->priv->netdev->reg_state == NETREG_REGISTERED)) in hfi1_ipoib_sdma_wakeup()
677 if (likely(dev->reg_state == NETREG_REGISTERED) && in hfi1_ipoib_flush_txq()
/openbmc/linux/net/openvswitch/
H A Dvport-netdev.c174 if (vport->dev->reg_state == NETREG_REGISTERED) in ovs_netdev_tunnel_destroy()
/openbmc/linux/net/caif/
H A Dcaif_usb.c137 if (what == NETDEV_UNREGISTER && dev->reg_state >= NETREG_UNREGISTERED) in cfusbl_device_notify()
/openbmc/linux/drivers/iio/light/
H A Dstk3310.c112 struct regmap_field *reg_state; member
451 ret = regmap_field_write(data->reg_state, state); in stk3310_set_state()
/openbmc/qemu/include/hw/cxl/
H A Dcxl_component.h256 void cxl_component_register_init_common(uint32_t *reg_state,
/openbmc/linux/net/can/
H A Draw.c569 if (dev->reg_state != NETREG_REGISTERED) { in raw_setsockopt()
629 if (dev->reg_state != NETREG_REGISTERED) { in raw_setsockopt()
/openbmc/linux/net/sched/
H A Dsch_generic.c588 if (dev->reg_state == NETREG_UNINITIALIZED) in netif_carrier_on()
607 if (dev->reg_state == NETREG_UNINITIALIZED) in netif_carrier_off()
625 if (dev->reg_state == NETREG_UNINITIALIZED) in netif_carrier_event()

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