211 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)  in ras_init_common()  argument
217     stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);  in ras_init_common()
220     stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);  in ras_init_common()
222     stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);  in ras_init_common()
224     stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);  in ras_init_common()
226     stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);  in ras_init_common()
229     stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);  in ras_init_common()
232 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,  in hdm_init_common()  argument
239     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,  in hdm_init_common()
241     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);  in hdm_init_common()
242     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);  in hdm_init_common()
243     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);  in hdm_init_common()
244     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,  in hdm_init_common()
246     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0);  in hdm_init_common()
247     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0);  in hdm_init_common()
248     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0);  in hdm_init_common()
249     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,  in hdm_init_common()
251     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0);  in hdm_init_common()
252     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,  in hdm_init_common()
254     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,  in hdm_init_common()
276 void cxl_component_register_init_common(uint32_t *reg_state,  in cxl_component_register_init_common()  argument
308     memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);  in cxl_component_register_init_common()
311     ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);  in cxl_component_register_init_common()
312     ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION,  in cxl_component_register_init_common()
314     ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);  in cxl_component_register_init_common()
315     ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);  in cxl_component_register_init_common()
320         reg_state[which] = FIELD_DP32(reg_state[which],                       \  in cxl_component_register_init_common()
322         reg_state[which] =                                                    \  in cxl_component_register_init_common()
323             FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER,       \  in cxl_component_register_init_common()
325         reg_state[which] =                                                    \  in cxl_component_register_init_common()
326             FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR,  \  in cxl_component_register_init_common()
338         ras_init_common(reg_state, write_msk);  in cxl_component_register_init_common()
352         hdm_init_common(reg_state, write_msk, type);  in cxl_component_register_init_common()