/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
H A D | irq_service_dcn201.c | 152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 153 .enable_reg = SRI(reg1, block, reg_num),\ 155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 160 .ack_reg = SRI(reg2, block, reg_num),\ 162 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 164 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 166 #define hpd_int_entry(reg_num)\ argument 167 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
H A D | irq_service_dce120.c | 103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 104 .enable_reg = SRI(reg1, block, reg_num),\ 106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 111 .ack_reg = SRI(reg2, block, reg_num),\ 113 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 117 #define hpd_int_entry(reg_num)\ argument 118 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
H A D | irq_service_dcn303.c | 119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 120 .enable_reg = SRI(reg1, block, reg_num),\ 121 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 123 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 124 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 126 .ack_reg = SRI(reg2, block, reg_num),\ 127 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 128 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 132 #define hpd_int_entry(reg_num)\ argument 133 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/ |
H A D | irq_service_dce80.c | 92 #define hpd_int_entry(reg_num)\ argument 93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 94 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 100 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 103 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 107 #define hpd_rx_int_entry(reg_num)\ argument 108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 109 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 114 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 117 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
H A D | irq_service_dcn10.c | 200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 201 .enable_reg = SRI(reg1, block, reg_num),\ 203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 208 .ack_reg = SRI(reg2, block, reg_num),\ 210 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 212 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 214 #define hpd_int_entry(reg_num)\ argument 215 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
H A D | irq_service_dcn20.c | 205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 206 .enable_reg = SRI(reg1, block, reg_num),\ 208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 211 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 213 .ack_reg = SRI(reg2, block, reg_num),\ 215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 221 #define hpd_int_entry(reg_num)\ argument 222 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | pcr.c | 55 static u64 direct_pcr_read(unsigned long reg_num) in direct_pcr_read() argument 59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read() 64 static void direct_pcr_write(unsigned long reg_num, u64 val) in direct_pcr_write() argument 66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write() 70 static u64 direct_pic_read(unsigned long reg_num) in direct_pic_read() argument 74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read() 79 static void direct_pic_write(unsigned long reg_num, u64 val) in direct_pic_write() argument 81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write() 111 static void n2_pcr_write(unsigned long reg_num, u64 val) in n2_pcr_write() argument 115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/ |
H A D | irq_service_dce60.c | 101 #define hpd_int_entry(reg_num)\ argument 102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 103 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 109 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 112 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 116 #define hpd_rx_int_entry(reg_num)\ argument 117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 118 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 123 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 126 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
H A D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 209 .enable_reg = SRI(reg1, block, reg_num),\ 211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 216 .ack_reg = SRI(reg2, block, reg_num),\ 218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 236 #define hpd_int_entry(reg_num)\ argument 237 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
H A D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 210 .enable_reg = SRI(reg1, block, reg_num),\ 212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 217 .ack_reg = SRI(reg2, block, reg_num),\ 219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 237 #define hpd_int_entry(reg_num)\ argument 238 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
H A D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 216 .enable_reg = SRI(reg1, block, reg_num),\ 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 223 .ack_reg = SRI(reg2, block, reg_num),\ 225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 243 #define hpd_int_entry(reg_num)\ argument 244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
H A D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 221 .enable_reg = SRI(reg1, block, reg_num),\ 223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 228 .ack_reg = SRI(reg2, block, reg_num),\ 230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 248 #define hpd_int_entry(reg_num)\ argument 249 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
H A D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 196 .enable_reg = SRI(reg1, block, reg_num),\ 197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 202 .ack_reg = SRI(reg2, block, reg_num),\ 203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 227 #define hpd_int_entry(reg_num)\ argument 228 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
H A D | irq_service_dcn21.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 216 .enable_reg = SRI(reg1, block, reg_num),\ 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 223 .ack_reg = SRI(reg2, block, reg_num),\ 225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 243 #define hpd_int_entry(reg_num)\ argument 244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
H A D | irq_service_dcn314.c | 210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 211 .enable_reg = SRI(reg1, block, reg_num),\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 218 .ack_reg = SRI(reg2, block, reg_num),\ 220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 238 #define hpd_int_entry(reg_num)\ argument 239 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
H A D | irq_service_dce110.c | 89 #define hpd_int_entry(reg_num)\ argument 90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 91 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 100 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ 104 #define hpd_rx_int_entry(reg_num)\ argument 105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 106 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 114 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ [all …]
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/openbmc/linux/arch/riscv/kvm/ |
H A D | vcpu_onereg.c | 124 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config() local 132 switch (reg_num) { in kvm_riscv_vcpu_get_reg_config() 173 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_config() local 184 switch (reg_num) { in kvm_riscv_vcpu_set_reg_config() 278 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_core() local 285 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_core() 288 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) in kvm_riscv_vcpu_get_reg_core() 290 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && in kvm_riscv_vcpu_get_reg_core() 291 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) in kvm_riscv_vcpu_get_reg_core() 292 reg_val = ((unsigned long *)cntx)[reg_num]; in kvm_riscv_vcpu_get_reg_core() [all …]
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H A D | vcpu_fp.c | 84 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_fp() local 93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp() 95 else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp() 96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp() 97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp() 102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp() 106 } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp() 107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp() 110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp() 129 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_fp() local [all …]
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H A D | vcpu_sbi.c | 139 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_single() argument 146 if (reg_num >= KVM_RISCV_SBI_EXT_MAX) in riscv_vcpu_set_sbi_ext_single() 153 if (sbi_ext[i].ext_idx == reg_num) { in riscv_vcpu_set_sbi_ext_single() 175 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_single() argument 182 if (reg_num >= KVM_RISCV_SBI_EXT_MAX) in riscv_vcpu_get_sbi_ext_single() 186 if (sbi_ext[i].ext_idx == reg_num) { in riscv_vcpu_get_sbi_ext_single() 208 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_multi() argument 213 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) in riscv_vcpu_set_sbi_ext_multi() 217 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_set_sbi_ext_multi() 228 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_multi() argument [all …]
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/openbmc/linux/drivers/video/fbdev/via/ |
H A D | hw.h | 355 int reg_num; member 361 int reg_num; member 367 int reg_num; member 373 int reg_num; member 379 int reg_num; member 385 int reg_num; member 391 int reg_num; member 397 int reg_num; member 403 int reg_num; member 409 int reg_num; member [all …]
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/openbmc/qemu/target/riscv/ |
H A D | translate.c | 330 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) in get_gpr() argument 334 if (reg_num == 0) { in get_gpr() 345 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in get_gpr() 349 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in get_gpr() 361 return cpu_gpr[reg_num]; in get_gpr() 364 static TCGv get_gprh(DisasContext *ctx, int reg_num) in get_gprh() argument 367 if (reg_num == 0) { in get_gprh() 370 return cpu_gprh[reg_num]; in get_gprh() 373 static TCGv dest_gpr(DisasContext *ctx, int reg_num) in dest_gpr() argument 375 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { in dest_gpr() [all …]
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/openbmc/qemu/target/loongarch/tcg/ |
H A D | translate.c | 171 static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext) in gpr_src() argument 175 if (reg_num == 0) { in gpr_src() 181 return cpu_gpr[reg_num]; in gpr_src() 184 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src() 188 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src() 194 static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext) in gpr_dst() argument 196 if (reg_num == 0 || dst_ext) { in gpr_dst() 199 return cpu_gpr[reg_num]; in gpr_dst() 202 static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext) in gen_set_gpr() argument 204 if (reg_num != 0) { in gen_set_gpr() [all …]
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzacas.c.inc | 31 static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) 37 if (reg_num == 0) { 42 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 46 static void gen_set_gpr_pair(DisasContext *ctx, int reg_num, TCGv_i64 t) 50 if (reg_num != 0) { 52 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 54 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 55 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 59 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 60 tcg_gen_sari_tl(cpu_gprh[reg_num + 1], cpu_gpr[reg_num + 1], 63);
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/openbmc/qemu/tests/qtest/libqos/ |
H A D | ahci.h | 517 static inline uint32_t ahci_rreg(AHCIQState *ahci, uint32_t reg_num) in ahci_rreg() argument 519 return ahci_mread(ahci, 4 * reg_num); in ahci_rreg() 522 static inline void ahci_wreg(AHCIQState *ahci, uint32_t reg_num, uint32_t value) in ahci_wreg() argument 524 ahci_mwrite(ahci, 4 * reg_num, value); in ahci_wreg() 527 static inline void ahci_set(AHCIQState *ahci, uint32_t reg_num, uint32_t mask) in ahci_set() argument 529 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) | mask); in ahci_set() 532 static inline void ahci_clr(AHCIQState *ahci, uint32_t reg_num, uint32_t mask) in ahci_clr() argument 534 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask); in ahci_clr() 537 static inline size_t ahci_px_offset(uint8_t port, uint32_t reg_num) in ahci_px_offset() argument 539 return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num; in ahci_px_offset() [all …]
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/openbmc/linux/drivers/irqchip/ |
H A D | irq-imx-irqsteer.c | 35 int reg_num; member 45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index() 56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask() 58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask() 70 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask() 72 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask() 146 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler() 150 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler() 196 data->reg_num = irqs_num / 32; in imx_irqsteer_probe() 200 sizeof(u32) * data->reg_num, in imx_irqsteer_probe() [all …]
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