xref: /openbmc/linux/drivers/irqchip/irq-imx-irqsteer.c (revision 7e24a55b2122746c2eef192296fc84624354f895)
10136afa0SLucas Stach // SPDX-License-Identifier: GPL-2.0+
20136afa0SLucas Stach /*
30136afa0SLucas Stach  * Copyright 2017 NXP
40136afa0SLucas Stach  * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
50136afa0SLucas Stach  */
60136afa0SLucas Stach 
70136afa0SLucas Stach #include <linux/clk.h>
80136afa0SLucas Stach #include <linux/interrupt.h>
90136afa0SLucas Stach #include <linux/irq.h>
100136afa0SLucas Stach #include <linux/irqchip/chained_irq.h>
110136afa0SLucas Stach #include <linux/irqdomain.h>
120136afa0SLucas Stach #include <linux/kernel.h>
13ee076750SRob Herring #include <linux/of.h>
1428528fcaSAisheng Dong #include <linux/of_irq.h>
15ee076750SRob Herring #include <linux/platform_device.h>
164730d223SLucas Stach #include <linux/pm_runtime.h>
170136afa0SLucas Stach #include <linux/spinlock.h>
180136afa0SLucas Stach 
19deb904e4SAisheng Dong #define CTRL_STRIDE_OFF(_t, _r)	(_t * 4 * _r)
200136afa0SLucas Stach #define CHANCTRL		0x0
210136afa0SLucas Stach #define CHANMASK(n, t)		(CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
220136afa0SLucas Stach #define CHANSET(n, t)		(CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
230136afa0SLucas Stach #define CHANSTATUS(n, t)	(CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
240136afa0SLucas Stach #define CHAN_MINTDIS(t)		(CTRL_STRIDE_OFF(t, 3) + 0x4)
250136afa0SLucas Stach #define CHAN_MASTRSTAT(t)	(CTRL_STRIDE_OFF(t, 3) + 0x8)
260136afa0SLucas Stach 
2728528fcaSAisheng Dong #define CHAN_MAX_OUTPUT_INT	0x8
2828528fcaSAisheng Dong 
290136afa0SLucas Stach struct irqsteer_data {
300136afa0SLucas Stach 	void __iomem		*regs;
310136afa0SLucas Stach 	struct clk		*ipg_clk;
3228528fcaSAisheng Dong 	int			irq[CHAN_MAX_OUTPUT_INT];
3328528fcaSAisheng Dong 	int			irq_count;
340136afa0SLucas Stach 	raw_spinlock_t		lock;
35deb904e4SAisheng Dong 	int			reg_num;
360136afa0SLucas Stach 	int			channel;
370136afa0SLucas Stach 	struct irq_domain	*domain;
380136afa0SLucas Stach 	u32			*saved_reg;
39*21bd3f9eSShenwei Wang 	struct device		*dev;
400136afa0SLucas Stach };
410136afa0SLucas Stach 
imx_irqsteer_get_reg_index(struct irqsteer_data * data,unsigned long irqnum)420136afa0SLucas Stach static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
430136afa0SLucas Stach 				      unsigned long irqnum)
440136afa0SLucas Stach {
45deb904e4SAisheng Dong 	return (data->reg_num - irqnum / 32 - 1);
460136afa0SLucas Stach }
470136afa0SLucas Stach 
imx_irqsteer_irq_unmask(struct irq_data * d)480136afa0SLucas Stach static void imx_irqsteer_irq_unmask(struct irq_data *d)
490136afa0SLucas Stach {
500136afa0SLucas Stach 	struct irqsteer_data *data = d->chip_data;
510136afa0SLucas Stach 	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
520136afa0SLucas Stach 	unsigned long flags;
530136afa0SLucas Stach 	u32 val;
540136afa0SLucas Stach 
550136afa0SLucas Stach 	raw_spin_lock_irqsave(&data->lock, flags);
56deb904e4SAisheng Dong 	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
570136afa0SLucas Stach 	val |= BIT(d->hwirq % 32);
58deb904e4SAisheng Dong 	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
590136afa0SLucas Stach 	raw_spin_unlock_irqrestore(&data->lock, flags);
600136afa0SLucas Stach }
610136afa0SLucas Stach 
imx_irqsteer_irq_mask(struct irq_data * d)620136afa0SLucas Stach static void imx_irqsteer_irq_mask(struct irq_data *d)
630136afa0SLucas Stach {
640136afa0SLucas Stach 	struct irqsteer_data *data = d->chip_data;
650136afa0SLucas Stach 	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
660136afa0SLucas Stach 	unsigned long flags;
670136afa0SLucas Stach 	u32 val;
680136afa0SLucas Stach 
690136afa0SLucas Stach 	raw_spin_lock_irqsave(&data->lock, flags);
70deb904e4SAisheng Dong 	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
710136afa0SLucas Stach 	val &= ~BIT(d->hwirq % 32);
72deb904e4SAisheng Dong 	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
730136afa0SLucas Stach 	raw_spin_unlock_irqrestore(&data->lock, flags);
740136afa0SLucas Stach }
750136afa0SLucas Stach 
imx_irqsteer_irq_bus_lock(struct irq_data * d)76*21bd3f9eSShenwei Wang static void imx_irqsteer_irq_bus_lock(struct irq_data *d)
77*21bd3f9eSShenwei Wang {
78*21bd3f9eSShenwei Wang 	struct irqsteer_data *data = d->chip_data;
79*21bd3f9eSShenwei Wang 
80*21bd3f9eSShenwei Wang 	pm_runtime_get_sync(data->dev);
81*21bd3f9eSShenwei Wang }
82*21bd3f9eSShenwei Wang 
imx_irqsteer_irq_bus_sync_unlock(struct irq_data * d)83*21bd3f9eSShenwei Wang static void imx_irqsteer_irq_bus_sync_unlock(struct irq_data *d)
84*21bd3f9eSShenwei Wang {
85*21bd3f9eSShenwei Wang 	struct irqsteer_data *data = d->chip_data;
86*21bd3f9eSShenwei Wang 
87*21bd3f9eSShenwei Wang 	pm_runtime_put_autosuspend(data->dev);
88*21bd3f9eSShenwei Wang }
89*21bd3f9eSShenwei Wang 
90e9a50f12SLucas Stach static const struct irq_chip imx_irqsteer_irq_chip = {
910136afa0SLucas Stach 	.name			= "irqsteer",
920136afa0SLucas Stach 	.irq_mask		= imx_irqsteer_irq_mask,
930136afa0SLucas Stach 	.irq_unmask		= imx_irqsteer_irq_unmask,
94*21bd3f9eSShenwei Wang 	.irq_bus_lock		= imx_irqsteer_irq_bus_lock,
95*21bd3f9eSShenwei Wang 	.irq_bus_sync_unlock	= imx_irqsteer_irq_bus_sync_unlock,
960136afa0SLucas Stach };
970136afa0SLucas Stach 
imx_irqsteer_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)980136afa0SLucas Stach static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
990136afa0SLucas Stach 				irq_hw_number_t hwirq)
1000136afa0SLucas Stach {
1010136afa0SLucas Stach 	irq_set_status_flags(irq, IRQ_LEVEL);
1020136afa0SLucas Stach 	irq_set_chip_data(irq, h->host_data);
1030136afa0SLucas Stach 	irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
1040136afa0SLucas Stach 
1050136afa0SLucas Stach 	return 0;
1060136afa0SLucas Stach }
1070136afa0SLucas Stach 
1080136afa0SLucas Stach static const struct irq_domain_ops imx_irqsteer_domain_ops = {
1090136afa0SLucas Stach 	.map		= imx_irqsteer_irq_map,
1100136afa0SLucas Stach 	.xlate		= irq_domain_xlate_onecell,
1110136afa0SLucas Stach };
1120136afa0SLucas Stach 
imx_irqsteer_get_hwirq_base(struct irqsteer_data * data,u32 irq)11328528fcaSAisheng Dong static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
11428528fcaSAisheng Dong {
11528528fcaSAisheng Dong 	int i;
11628528fcaSAisheng Dong 
11728528fcaSAisheng Dong 	for (i = 0; i < data->irq_count; i++) {
11828528fcaSAisheng Dong 		if (data->irq[i] == irq)
11928528fcaSAisheng Dong 			return i * 64;
12028528fcaSAisheng Dong 	}
12128528fcaSAisheng Dong 
12228528fcaSAisheng Dong 	return -EINVAL;
12328528fcaSAisheng Dong }
12428528fcaSAisheng Dong 
imx_irqsteer_irq_handler(struct irq_desc * desc)1250136afa0SLucas Stach static void imx_irqsteer_irq_handler(struct irq_desc *desc)
1260136afa0SLucas Stach {
1270136afa0SLucas Stach 	struct irqsteer_data *data = irq_desc_get_handler_data(desc);
12828528fcaSAisheng Dong 	int hwirq;
12928528fcaSAisheng Dong 	int irq, i;
1300136afa0SLucas Stach 
1310136afa0SLucas Stach 	chained_irq_enter(irq_desc_get_chip(desc), desc);
1320136afa0SLucas Stach 
13328528fcaSAisheng Dong 	irq = irq_desc_get_irq(desc);
13428528fcaSAisheng Dong 	hwirq = imx_irqsteer_get_hwirq_base(data, irq);
13528528fcaSAisheng Dong 	if (hwirq < 0) {
13628528fcaSAisheng Dong 		pr_warn("%s: unable to get hwirq base for irq %d\n",
13728528fcaSAisheng Dong 			__func__, irq);
13828528fcaSAisheng Dong 		return;
13928528fcaSAisheng Dong 	}
14028528fcaSAisheng Dong 
14128528fcaSAisheng Dong 	for (i = 0; i < 2; i++, hwirq += 32) {
14228528fcaSAisheng Dong 		int idx = imx_irqsteer_get_reg_index(data, hwirq);
1430136afa0SLucas Stach 		unsigned long irqmap;
144046a6ee2SMarc Zyngier 		int pos;
1450136afa0SLucas Stach 
14628528fcaSAisheng Dong 		if (hwirq >= data->reg_num * 32)
14728528fcaSAisheng Dong 			break;
14828528fcaSAisheng Dong 
1490136afa0SLucas Stach 		irqmap = readl_relaxed(data->regs +
150deb904e4SAisheng Dong 				       CHANSTATUS(idx, data->reg_num));
1510136afa0SLucas Stach 
152046a6ee2SMarc Zyngier 		for_each_set_bit(pos, &irqmap, 32)
153046a6ee2SMarc Zyngier 			generic_handle_domain_irq(data->domain, pos + hwirq);
1540136afa0SLucas Stach 	}
1550136afa0SLucas Stach 
1560136afa0SLucas Stach 	chained_irq_exit(irq_desc_get_chip(desc), desc);
1570136afa0SLucas Stach }
1580136afa0SLucas Stach 
imx_irqsteer_probe(struct platform_device * pdev)1590136afa0SLucas Stach static int imx_irqsteer_probe(struct platform_device *pdev)
1600136afa0SLucas Stach {
1610136afa0SLucas Stach 	struct device_node *np = pdev->dev.of_node;
1620136afa0SLucas Stach 	struct irqsteer_data *data;
16328528fcaSAisheng Dong 	u32 irqs_num;
16428528fcaSAisheng Dong 	int i, ret;
1650136afa0SLucas Stach 
1660136afa0SLucas Stach 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1670136afa0SLucas Stach 	if (!data)
1680136afa0SLucas Stach 		return -ENOMEM;
1690136afa0SLucas Stach 
170*21bd3f9eSShenwei Wang 	data->dev = &pdev->dev;
171358b9d24SAnson Huang 	data->regs = devm_platform_ioremap_resource(pdev, 0);
1720136afa0SLucas Stach 	if (IS_ERR(data->regs)) {
1730136afa0SLucas Stach 		dev_err(&pdev->dev, "failed to initialize reg\n");
1740136afa0SLucas Stach 		return PTR_ERR(data->regs);
1750136afa0SLucas Stach 	}
1760136afa0SLucas Stach 
1770136afa0SLucas Stach 	data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
178e0c45b10SAnson Huang 	if (IS_ERR(data->ipg_clk))
179e0c45b10SAnson Huang 		return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
180e0c45b10SAnson Huang 				     "failed to get ipg clk\n");
1810136afa0SLucas Stach 
1820136afa0SLucas Stach 	raw_spin_lock_init(&data->lock);
1830136afa0SLucas Stach 
1847d3a5eb7SArnd Bergmann 	ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
1857d3a5eb7SArnd Bergmann 	if (ret)
1867d3a5eb7SArnd Bergmann 		return ret;
1877d3a5eb7SArnd Bergmann 	ret = of_property_read_u32(np, "fsl,channel", &data->channel);
1887d3a5eb7SArnd Bergmann 	if (ret)
1897d3a5eb7SArnd Bergmann 		return ret;
1900136afa0SLucas Stach 
19128528fcaSAisheng Dong 	/*
19228528fcaSAisheng Dong 	 * There is one output irq for each group of 64 inputs.
19328528fcaSAisheng Dong 	 * One register bit map can represent 32 input interrupts.
19428528fcaSAisheng Dong 	 */
19528528fcaSAisheng Dong 	data->irq_count = DIV_ROUND_UP(irqs_num, 64);
19628528fcaSAisheng Dong 	data->reg_num = irqs_num / 32;
197deb904e4SAisheng Dong 
1984730d223SLucas Stach 	if (IS_ENABLED(CONFIG_PM)) {
1990136afa0SLucas Stach 		data->saved_reg = devm_kzalloc(&pdev->dev,
200deb904e4SAisheng Dong 					sizeof(u32) * data->reg_num,
2010136afa0SLucas Stach 					GFP_KERNEL);
2020136afa0SLucas Stach 		if (!data->saved_reg)
2030136afa0SLucas Stach 			return -ENOMEM;
2040136afa0SLucas Stach 	}
2050136afa0SLucas Stach 
2060136afa0SLucas Stach 	ret = clk_prepare_enable(data->ipg_clk);
2070136afa0SLucas Stach 	if (ret) {
2080136afa0SLucas Stach 		dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2090136afa0SLucas Stach 		return ret;
2100136afa0SLucas Stach 	}
2110136afa0SLucas Stach 
2120136afa0SLucas Stach 	/* steer all IRQs into configured channel */
2130136afa0SLucas Stach 	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
2140136afa0SLucas Stach 
215deb904e4SAisheng Dong 	data->domain = irq_domain_add_linear(np, data->reg_num * 32,
2160136afa0SLucas Stach 					     &imx_irqsteer_domain_ops, data);
2170136afa0SLucas Stach 	if (!data->domain) {
2180136afa0SLucas Stach 		dev_err(&pdev->dev, "failed to create IRQ domain\n");
21928528fcaSAisheng Dong 		ret = -ENOMEM;
22028528fcaSAisheng Dong 		goto out;
2210136afa0SLucas Stach 	}
2224730d223SLucas Stach 	irq_domain_set_pm_device(data->domain, &pdev->dev);
2230136afa0SLucas Stach 
22428528fcaSAisheng Dong 	if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
22528528fcaSAisheng Dong 		ret = -EINVAL;
22628528fcaSAisheng Dong 		goto out;
22728528fcaSAisheng Dong 	}
22828528fcaSAisheng Dong 
22928528fcaSAisheng Dong 	for (i = 0; i < data->irq_count; i++) {
23028528fcaSAisheng Dong 		data->irq[i] = irq_of_parse_and_map(np, i);
23128528fcaSAisheng Dong 		if (!data->irq[i]) {
23228528fcaSAisheng Dong 			ret = -EINVAL;
23328528fcaSAisheng Dong 			goto out;
23428528fcaSAisheng Dong 		}
23528528fcaSAisheng Dong 
23628528fcaSAisheng Dong 		irq_set_chained_handler_and_data(data->irq[i],
23728528fcaSAisheng Dong 						 imx_irqsteer_irq_handler,
2380136afa0SLucas Stach 						 data);
23928528fcaSAisheng Dong 	}
2400136afa0SLucas Stach 
2410136afa0SLucas Stach 	platform_set_drvdata(pdev, data);
2420136afa0SLucas Stach 
2434730d223SLucas Stach 	pm_runtime_set_active(&pdev->dev);
2444730d223SLucas Stach 	pm_runtime_enable(&pdev->dev);
2454730d223SLucas Stach 
2460136afa0SLucas Stach 	return 0;
24728528fcaSAisheng Dong out:
24828528fcaSAisheng Dong 	clk_disable_unprepare(data->ipg_clk);
24928528fcaSAisheng Dong 	return ret;
2500136afa0SLucas Stach }
2510136afa0SLucas Stach 
imx_irqsteer_remove(struct platform_device * pdev)2520136afa0SLucas Stach static int imx_irqsteer_remove(struct platform_device *pdev)
2530136afa0SLucas Stach {
2540136afa0SLucas Stach 	struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
25528528fcaSAisheng Dong 	int i;
2560136afa0SLucas Stach 
25728528fcaSAisheng Dong 	for (i = 0; i < irqsteer_data->irq_count; i++)
25828528fcaSAisheng Dong 		irq_set_chained_handler_and_data(irqsteer_data->irq[i],
25928528fcaSAisheng Dong 						 NULL, NULL);
26028528fcaSAisheng Dong 
2610136afa0SLucas Stach 	irq_domain_remove(irqsteer_data->domain);
2620136afa0SLucas Stach 
2630136afa0SLucas Stach 	clk_disable_unprepare(irqsteer_data->ipg_clk);
2640136afa0SLucas Stach 
2650136afa0SLucas Stach 	return 0;
2660136afa0SLucas Stach }
2670136afa0SLucas Stach 
2684730d223SLucas Stach #ifdef CONFIG_PM
imx_irqsteer_save_regs(struct irqsteer_data * data)2690136afa0SLucas Stach static void imx_irqsteer_save_regs(struct irqsteer_data *data)
2700136afa0SLucas Stach {
2710136afa0SLucas Stach 	int i;
2720136afa0SLucas Stach 
273deb904e4SAisheng Dong 	for (i = 0; i < data->reg_num; i++)
2740136afa0SLucas Stach 		data->saved_reg[i] = readl_relaxed(data->regs +
275deb904e4SAisheng Dong 						CHANMASK(i, data->reg_num));
2760136afa0SLucas Stach }
2770136afa0SLucas Stach 
imx_irqsteer_restore_regs(struct irqsteer_data * data)2780136afa0SLucas Stach static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
2790136afa0SLucas Stach {
2800136afa0SLucas Stach 	int i;
2810136afa0SLucas Stach 
2820136afa0SLucas Stach 	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
283deb904e4SAisheng Dong 	for (i = 0; i < data->reg_num; i++)
2840136afa0SLucas Stach 		writel_relaxed(data->saved_reg[i],
285deb904e4SAisheng Dong 			       data->regs + CHANMASK(i, data->reg_num));
2860136afa0SLucas Stach }
2870136afa0SLucas Stach 
imx_irqsteer_suspend(struct device * dev)2880136afa0SLucas Stach static int imx_irqsteer_suspend(struct device *dev)
2890136afa0SLucas Stach {
2900136afa0SLucas Stach 	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
2910136afa0SLucas Stach 
2920136afa0SLucas Stach 	imx_irqsteer_save_regs(irqsteer_data);
2930136afa0SLucas Stach 	clk_disable_unprepare(irqsteer_data->ipg_clk);
2940136afa0SLucas Stach 
2950136afa0SLucas Stach 	return 0;
2960136afa0SLucas Stach }
2970136afa0SLucas Stach 
imx_irqsteer_resume(struct device * dev)2980136afa0SLucas Stach static int imx_irqsteer_resume(struct device *dev)
2990136afa0SLucas Stach {
3000136afa0SLucas Stach 	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
3010136afa0SLucas Stach 	int ret;
3020136afa0SLucas Stach 
3030136afa0SLucas Stach 	ret = clk_prepare_enable(irqsteer_data->ipg_clk);
3040136afa0SLucas Stach 	if (ret) {
3050136afa0SLucas Stach 		dev_err(dev, "failed to enable ipg clk: %d\n", ret);
3060136afa0SLucas Stach 		return ret;
3070136afa0SLucas Stach 	}
3080136afa0SLucas Stach 	imx_irqsteer_restore_regs(irqsteer_data);
3090136afa0SLucas Stach 
3100136afa0SLucas Stach 	return 0;
3110136afa0SLucas Stach }
3120136afa0SLucas Stach #endif
3130136afa0SLucas Stach 
3140136afa0SLucas Stach static const struct dev_pm_ops imx_irqsteer_pm_ops = {
3154730d223SLucas Stach 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
3164730d223SLucas Stach 				      pm_runtime_force_resume)
3174730d223SLucas Stach 	SET_RUNTIME_PM_OPS(imx_irqsteer_suspend,
3184730d223SLucas Stach 			   imx_irqsteer_resume, NULL)
3190136afa0SLucas Stach };
3200136afa0SLucas Stach 
3210136afa0SLucas Stach static const struct of_device_id imx_irqsteer_dt_ids[] = {
3220136afa0SLucas Stach 	{ .compatible = "fsl,imx-irqsteer", },
3230136afa0SLucas Stach 	{},
3240136afa0SLucas Stach };
3250136afa0SLucas Stach 
3260136afa0SLucas Stach static struct platform_driver imx_irqsteer_driver = {
3270136afa0SLucas Stach 	.driver = {
3280136afa0SLucas Stach 		.name = "imx-irqsteer",
3290136afa0SLucas Stach 		.of_match_table = imx_irqsteer_dt_ids,
3300136afa0SLucas Stach 		.pm = &imx_irqsteer_pm_ops,
3310136afa0SLucas Stach 	},
3320136afa0SLucas Stach 	.probe = imx_irqsteer_probe,
3330136afa0SLucas Stach 	.remove = imx_irqsteer_remove,
3340136afa0SLucas Stach };
3350136afa0SLucas Stach builtin_platform_driver(imx_irqsteer_driver);
336