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Searched refs:reg_ctrl (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dmcu_mpc8349emitx.c37 u8 reg_ctrl; member
52 mcu->reg_ctrl = ret; in shutdown_thread_fn()
55 if (mcu->reg_ctrl & MCU_CTRL_BTN) { in shutdown_thread_fn()
57 mcu->reg_ctrl & ~MCU_CTRL_BTN); in shutdown_thread_fn()
78 mcu->reg_ctrl = ret; in show_status()
91 mcu->reg_ctrl | MCU_CTRL_POFF); in mcu_power_off()
102 mcu->reg_ctrl &= ~bit; in mcu_gpio_set()
104 mcu->reg_ctrl |= bit; in mcu_gpio_set()
106 i2c_smbus_write_byte_data(mcu->client, MCU_REG_CTRL, mcu->reg_ctrl); in mcu_gpio_set()
155 mcu->reg_ctrl = ret; in mcu_probe()
/openbmc/linux/drivers/thermal/
H A Dloongson2_thermal.c41 u64 reg_ctrl = 0; in loongson2_thermal_set() local
50 reg_ctrl = low; in loongson2_thermal_set()
51 reg_ctrl |= enable ? 0x100 : 0; in loongson2_thermal_set()
52 writew(reg_ctrl, data->regs + LOONGSON2_THSENS_CTRL_LOW_REG + reg_off); in loongson2_thermal_set()
54 reg_ctrl = high; in loongson2_thermal_set()
55 reg_ctrl |= enable ? 0x100 : 0; in loongson2_thermal_set()
56 writew(reg_ctrl, data->regs + LOONGSON2_THSENS_CTRL_HI_REG + reg_off); in loongson2_thermal_set()
/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c133 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
145 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
146 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
147 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
148 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
170 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
172 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
201 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
202 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra210_peq.c59 static void tegra210_peq_read_ram(struct regmap *regmap, unsigned int reg_ctrl, in tegra210_peq_read_ram() argument
71 regmap_write(regmap, reg_ctrl, val); in tegra210_peq_read_ram()
81 static void tegra210_peq_write_ram(struct regmap *regmap, unsigned int reg_ctrl, in tegra210_peq_write_ram() argument
93 regmap_write(regmap, reg_ctrl, val); in tegra210_peq_write_ram()
152 u32 i, reg_ctrl = params->soc.base; in tegra210_peq_ram_get() local
153 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_peq_ram_get()
158 tegra210_peq_read_ram(ope->peq_regmap, reg_ctrl, reg_data, in tegra210_peq_ram_get()
175 u32 i, reg_ctrl = params->soc.base; in tegra210_peq_ram_put() local
176 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_peq_ram_put()
184 tegra210_peq_write_ram(ope->peq_regmap, reg_ctrl, reg_data, in tegra210_peq_ram_put()
H A Dtegra210_mbdrc.c215 static void tegra210_mbdrc_write_ram(struct regmap *regmap, unsigned int reg_ctrl, in tegra210_mbdrc_write_ram() argument
227 regmap_write(regmap, reg_ctrl, val); in tegra210_mbdrc_write_ram()
429 u32 reg_ctrl = params->soc.base; in tegra210_mbdrc_biquad_coeffs_put() local
430 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_mbdrc_biquad_coeffs_put()
433 tegra210_mbdrc_write_ram(ope->mbdrc_regmap, reg_ctrl, reg_data, in tegra210_mbdrc_biquad_coeffs_put()
/openbmc/linux/drivers/net/can/flexcan/
H A Dflexcan-core.c578 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_enable() local
580 priv->write(reg_ctrl, &regs->ctrl); in flexcan_error_irq_enable()
586 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_disable() local
588 priv->write(reg_ctrl, &regs->ctrl); in flexcan_error_irq_disable()
950 u32 reg_ctrl, reg_id, reg_iflag1; in flexcan_mailbox_read() local
959 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
960 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); in flexcan_mailbox_read()
963 code = reg_ctrl & FLEXCAN_MB_CODE_MASK; in flexcan_mailbox_read()
978 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
986 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) in flexcan_mailbox_read()
[all …]
/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23885-i2c.c84 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); in i2c_sendbytes()
107 cx_write(bus->reg_ctrl, ctrl); in i2c_sendbytes()
129 cx_write(bus->reg_ctrl, ctrl); in i2c_sendbytes()
163 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1); in i2c_readbytes()
189 cx_write(bus->reg_ctrl, ctrl); in i2c_readbytes()
H A Dcx23885.h241 u32 reg_ctrl; member
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-i2c.c83 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); in i2c_sendbytes()
108 cx_write(bus->reg_ctrl, ctrl); in i2c_sendbytes()
134 cx_write(bus->reg_ctrl, ctrl); in i2c_sendbytes()
174 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1); in i2c_readbytes()
199 cx_write(bus->reg_ctrl, ctrl); in i2c_readbytes()
H A Dcx25821.h149 u32 reg_ctrl; member
/openbmc/linux/drivers/gpu/drm/tiny/
H A Darcpgu.c122 u32 reg_ctrl; in arc_pgu_set_pxl_fmt() local
132 reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL); in arc_pgu_set_pxl_fmt()
134 reg_ctrl &= ~ARCPGU_MODE_XRGB8888; in arc_pgu_set_pxl_fmt()
136 reg_ctrl |= ARCPGU_MODE_XRGB8888; in arc_pgu_set_pxl_fmt()
137 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl); in arc_pgu_set_pxl_fmt()
/openbmc/linux/drivers/spi/
H A Dspi-ath79.c43 u32 reg_ctrl; member
90 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); in ath79_spi_enable()
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); in ath79_spi_disable()
/openbmc/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_drm_ade.c350 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; in ade_rdma_dump_regs() local
353 reg_ctrl = RD_CH_CTRL(ch); in ade_rdma_dump_regs()
362 val = readl(base + reg_ctrl); in ade_rdma_dump_regs()
552 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; in ade_rdma_set() local
563 reg_ctrl = RD_CH_CTRL(ch); in ade_rdma_set()
573 writel((fmt << 16) & 0x1f0000, base + reg_ctrl); in ade_rdma_set()
/openbmc/linux/tools/perf/util/cs-etm-decoder/
H A Dcs-etm-decoder.h27 u32 reg_ctrl; member
H A Dcs-etm-decoder.c142 config->reg_ctrl = params->etmv3.reg_ctrl; in cs_etm_decoder__gen_etmv3_config()
/openbmc/linux/sound/soc/fsl/
H A Dfsl_xcvr.c1164 void __iomem *reg_ctrl, *reg_buff; in irq0_isr() local
1179 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; in irq0_isr()
1181 memcpy_fromio(&val, reg_ctrl, sizeof(val)); in irq0_isr()
1183 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; in irq0_isr()
1185 memcpy_fromio(&val, reg_ctrl, sizeof(val)); in irq0_isr()
1198 memset_io(reg_ctrl, 0, sizeof(val)); in irq0_isr()
/openbmc/linux/drivers/misc/lis3lv02d/
H A Dlis3lv02d.h267 int (*reg_ctrl) (struct lis3lv02d *lis3, bool state); member
H A Dlis3lv02d.c394 if (lis3->reg_ctrl) in lis3lv02d_poweroff()
398 if (lis3->reg_ctrl) in lis3lv02d_poweroff()
399 lis3->reg_ctrl(lis3, LIS3_REG_OFF); in lis3lv02d_poweroff()
437 if (lis3->reg_ctrl) in lis3lv02d_poweron()
H A Dlis3lv02d_i2c.c153 lis3_dev.reg_ctrl = lis3_reg_ctrl; in lis3lv02d_i2c_probe()
/openbmc/linux/drivers/net/wireless/ath/wcn36xx/
H A Ddxe.c124 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L; in wcn36xx_dxe_alloc_ctl_blks()
125 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H; in wcn36xx_dxe_alloc_ctl_blks()
844 ch->reg_ctrl, ch->def_ctrl); in wcn36xx_dxe_tx_frame()
H A Ddxe.h443 u32 reg_ctrl; member
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvi.c1057 u32 reg_ctrl; in vi_set_vce_clocks() local
1063 reg_ctrl = ixGNB_CLK3_DFS_CNTL; in vi_set_vce_clocks()
1068 reg_ctrl = ixCG_ECLK_CNTL; in vi_set_vce_clocks()
1089 tmp = RREG32_SMC(reg_ctrl); in vi_set_vce_clocks()
1092 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay.h139 u32 reg_ctrl; /* 0x870 */ member
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c831 u32 reg, reg_ctrl, reg_ctrl2; in dsi_update_dsc_timing() local
869 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); in dsi_update_dsc_timing()
872 reg_ctrl &= ~0xffff; in dsi_update_dsc_timing()
873 reg_ctrl |= reg; in dsi_update_dsc_timing()
878 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); in dsi_update_dsc_timing()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c60 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) in modify_dg_result() argument
69 val_ctrl = readl(reg_ctrl); in modify_dg_result()
84 writel(val_ctrl, reg_ctrl); in modify_dg_result()

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