| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_dfs.c | 70 u32 reg; in wait_refresh_op_complete() local
74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
116 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
134 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
143 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
145 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
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| H A D | ddr3_write_leveling.c | 66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
75 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
76 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
79 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
83 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
85 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
89 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | asm-eva.h | 19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
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| /openbmc/linux/arch/parisc/include/asm/ |
| H A D | asmregs.h | 11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
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| /openbmc/u-boot/drivers/video/exynos/ |
| H A D | exynos_dp_lowlevel.c | 22 unsigned int reg; in exynos_dp_enable_video_input() local
24 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
25 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
29 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
31 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
39 unsigned int reg; in exynos_dp_enable_video_bist() local
41 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
42 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
46 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
48 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
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| H A D | exynos_mipi_dsi_lowlevel.c | 20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
29 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
44 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
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| /openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_reg.c | 28 u32 reg; in analogix_dp_enable_video_mute() local
31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
32 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
36 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
43 u32 reg; in analogix_dp_stop_video() local
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
46 reg &= ~VIDEO_EN; in analogix_dp_stop_video()
[all …]
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| /openbmc/linux/tools/testing/selftests/powerpc/include/ |
| H A D | vmx_asm.h | 9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
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| /openbmc/linux/drivers/media/platform/samsung/s5p-jpeg/ |
| H A D | jpeg-hw-s5p.c | 19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
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| H A D | jpeg-hw-exynos4.c | 18 unsigned int reg; in exynos4_jpeg_sw_reset() local
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
[all …]
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| H A D | jpeg-hw-exynos3250.c | 20 u32 reg = 1; in exynos3250_jpeg_reset() local
25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
31 reg = 0; in exynos3250_jpeg_reset()
34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
62 u32 reg; in exynos3250_jpeg_clk_set() local
64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
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| /openbmc/linux/drivers/media/cec/platform/s5p/ |
| H A D | exynos_hdmi_cecctrl.c | 26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
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| /openbmc/linux/drivers/scsi/qla2xxx/ |
| H A D | qla_dbg.c | 107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
118 if (qla_pci_disconnected(vha, reg)) in qla27xx_dump_mpi_ram()
125 wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(®->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(®->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
129 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
132 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
134 wrt_reg_word(®->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | tegra210.c | 21 .reg = 0x228,
25 .reg = 0x2e8,
37 .reg = 0x228,
41 .reg = 0x2f4,
53 .reg = 0x228,
57 .reg = 0x2e8,
69 .reg = 0x228,
73 .reg = 0x2f4,
85 .reg = 0x228,
89 .reg = 0x2ec,
[all …]
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| H A D | tegra114.c | 20 .reg = 0x34c,
32 .reg = 0x228,
36 .reg = 0x2e8,
48 .reg = 0x228,
52 .reg = 0x2f4,
64 .reg = 0x228,
68 .reg = 0x2e8,
80 .reg = 0x228,
84 .reg = 0x2f4,
96 .reg = 0x228,
[all …]
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| H A D | tegra124.c | 21 .reg = 0x34c,
33 .reg = 0x228,
37 .reg = 0x2e8,
49 .reg = 0x228,
53 .reg = 0x2f4,
65 .reg = 0x228,
69 .reg = 0x2e8,
81 .reg = 0x228,
85 .reg = 0x2f4,
97 .reg = 0x228,
[all …]
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| /openbmc/linux/tools/perf/util/ |
| H A D | amd-sample-raw.c | 23 static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg) in pr_ibs_fetch_ctl() argument
50 if (reg.phy_addr_valid) in pr_ibs_fetch_ctl()
51 l1tlb_pgsz_str = l1tlb_pgsz_strs_erratum1347[reg.l1tlb_pgsz]; in pr_ibs_fetch_ctl()
53 if (reg.phy_addr_valid) in pr_ibs_fetch_ctl()
54 l1tlb_pgsz_str = l1tlb_pgsz_strs[reg.l1tlb_pgsz]; in pr_ibs_fetch_ctl()
55 ic_miss_str = ic_miss_strs[reg.ic_miss]; in pr_ibs_fetch_ctl()
61 reg.l3_miss_only, reg.fetch_oc_miss, reg.fetch_l3_miss); in pr_ibs_fetch_ctl()
66 reg.val, reg.fetch_maxcnt << 4, reg.fetch_cnt << 4, reg.fetch_lat, in pr_ibs_fetch_ctl()
67 reg.fetch_en, reg.fetch_val, reg.fetch_comp, ic_miss_str ? : "", in pr_ibs_fetch_ctl()
68 reg.phy_addr_valid, l1tlb_pgsz_str ? : "", reg.l1tlb_miss, reg.l2tlb_miss, in pr_ibs_fetch_ctl()
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-38x-controlcenterdc.dts | 59 reg = <0x00000000 0x10000000>; /* 256 MB */
81 reg = <0x21>;
88 reg = <0x22>;
94 reg = <0x23>;
100 reg = <0x24>;
106 reg = <0x25>;
112 reg = <0x26>;
123 reg = <0x29>;
130 reg = <0x2d>;
132 reg = <0>;
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| /openbmc/linux/drivers/net/ethernet/sfc/ |
| H A D | io.h | 54 static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) in efx_reg() argument
56 return efx->reg_base + reg; in efx_reg()
61 unsigned int reg) in _efx_writeq() argument
63 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
65 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument
67 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq()
72 unsigned int reg) in _efx_writed() argument
74 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
76 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument
78 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd()
[all …]
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| /openbmc/linux/drivers/video/fbdev/riva/ |
| H A D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc15_common.h | 36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
43 WREG32(reg, value))
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
48 RREG32(reg))
50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument
[all …]
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| /openbmc/linux/drivers/net/ethernet/microchip/ |
| H A D | encx24j600-regmap.c | 60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
71 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
81 switch (reg) { in regmap_encx24j600_sfr_read()
104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
120 { .tx_buf = ®, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]
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| /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_dcb_82598.c | 23 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
28 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
29 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
31 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
33 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
35 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
37 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
39 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
46 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
49 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot_avp.c | 34 u32 reg; in wb_start() local
42 : "=r"(reg) /* output */ in wb_start()
46 if (reg != NV_WB_RUN_ADDRESS) in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
56 reg |= SWR_CSITE_RST; in wb_start()
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
68 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
76 reg |= CPU_CLMP; in wb_start()
[all …]
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| /openbmc/linux/drivers/media/platform/nxp/imx-jpeg/ |
| H A D | mxc-jpeg-hw.c | 35 void print_cast_status(struct device *dev, void __iomem *reg, in print_cast_status() argument
39 print_wrapper_reg(dev, reg, CAST_STATUS0); in print_cast_status()
40 print_wrapper_reg(dev, reg, CAST_STATUS1); in print_cast_status()
41 print_wrapper_reg(dev, reg, CAST_STATUS2); in print_cast_status()
42 print_wrapper_reg(dev, reg, CAST_STATUS3); in print_cast_status()
43 print_wrapper_reg(dev, reg, CAST_STATUS4); in print_cast_status()
44 print_wrapper_reg(dev, reg, CAST_STATUS5); in print_cast_status()
45 print_wrapper_reg(dev, reg, CAST_STATUS6); in print_cast_status()
46 print_wrapper_reg(dev, reg, CAST_STATUS7); in print_cast_status()
47 print_wrapper_reg(dev, reg, CAST_STATUS8); in print_cast_status()
[all …]
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