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Searched refs:refdiv (Results 1 – 25 of 40) sorted by relevance

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/openbmc/linux/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
60 refdiv = (val >> (pll->shift + 9)) & 0x1f; in mmp_clk_pll_recalc_rate()
63 refdiv = 1; in mmp_clk_pll_recalc_rate()
75 do_div(rate, refdiv); in mmp_clk_pll_recalc_rate()
79 if (refdiv == 3) { in mmp_clk_pll_recalc_rate()
81 } else if (refdiv == 4) { in mmp_clk_pll_recalc_rate()
84 pr_err("bad refdiv: %d (0x%08x)\n", refdiv, val); in mmp_clk_pll_recalc_rate()
89 do_div(rate, refdiv + 2); in mmp_clk_pll_recalc_rate()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c30 .refdiv = _refdiv,\
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
78 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
111 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
112 fref_khz = ref_khz / refdiv; in pll_para_config()
127 div->refdiv = refdiv; in pll_para_config()
241 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
270 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
H A Dclk_rk322x.c29 .refdiv = _refdiv,\
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
67 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
H A Dclk_rk3036.c32 .refdiv = _refdiv,\
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
69 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
202 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rk3399.c33 u32 refdiv; member
45 .refdiv = _refdiv,\
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
346 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
392 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
393 fref_khz = ref_khz / refdiv; in pll_para_config()
408 div->refdiv = refdiv; in pll_para_config()
839 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; in rk3399_ddr_set_clk()
[all …]
H A Dclk_rv1108.c32 .refdiv = _refdiv,\
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
99 (div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rk3328.c21 u32 refdiv; member
33 .refdiv = _refdiv,\
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
269 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c31 u8 refdiv; member
144 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
153 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
232 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz() local
240 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
247 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz() local
255 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-pll.c151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
173 do_div(rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
179 do_div(frac_rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
629 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
655 do_div(rate64, cur.refdiv); in rockchip_rk3399_pll_recalc_rate()
[all …]
/openbmc/linux/arch/mips/ath25/
H A Dar2315.c207 unsigned int pllc_out, refdiv, fdiv, divby2; in ar2315_sys_clk() local
211 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); in ar2315_sys_clk()
212 refdiv = clockctl1_predivide_table[refdiv]; in ar2315_sys_clk()
215 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; in ar2315_sys_clk()
/openbmc/linux/drivers/clk/pistachio/
H A Dclk-pll.c206 if (!params || !params->refdiv) in pll_gf40lp_frac_set_rate()
212 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
218 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
229 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_frac_set_rate()
363 if (!params || !params->refdiv) in pll_gf40lp_laint_set_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
371 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
397 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c175 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
193 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_main_vco_clk_hz()
199 vco = fref / refdiv; in cm_get_main_vco_clk_hz()
206 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
224 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_per_vco_clk_hz()
230 vco = fref / refdiv; in cm_get_per_vco_clk_hz()
/openbmc/linux/drivers/clk/visconti/
H A Dpll.h30 .refdiv = _refdiv, \
41 unsigned int refdiv; member
H A Dpll.c68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
138 writel(rate_table->refdiv, pll->pll_base + PLL_REFDIV_REG); in visconti_pll_set_params()
/openbmc/linux/drivers/clk/berlin/
H A Dberlin2-avpll.c159 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
164 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
165 refdiv = vco_refdiv[refdiv]; in berlin2_avpll_vco_recalc_rate()
168 do_div(freq, refdiv); in berlin2_avpll_vco_recalc_rate()
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c489 .refdiv = 0,
497 .refdiv = 0,
505 .refdiv = 0,
513 .refdiv = 0,
521 .refdiv = 0,
529 .refdiv = 0,
537 .refdiv = 0,
545 .refdiv = 0,
822 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
/openbmc/linux/drivers/media/dvb-frontends/
H A Dcx24113.c85 u8 refdiv; member
281 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) in cx24113_set_ref_div() argument
284 refdiv = 2; in cx24113_set_ref_div()
285 return state->refdiv = refdiv; in cx24113_set_ref_div()
396 cx24113_set_nfr(state, n, f, state->refdiv); in cx24113_set_frequency()
/openbmc/linux/sound/soc/codecs/
H A Darizona.c2099 int refdiv; member
2156 int refdiv, div; in arizona_calc_fratio() local
2160 cfg->refdiv = 0; in arizona_calc_fratio()
2164 cfg->refdiv++; in arizona_calc_fratio()
2196 refdiv = cfg->refdiv; in arizona_calc_fratio()
2199 init_ratio, Fref, refdiv); in arizona_calc_fratio()
2207 cfg->refdiv = refdiv; in arizona_calc_fratio()
2211 Fref, refdiv, div, ratio); in arizona_calc_fratio()
2233 cfg->refdiv = refdiv; in arizona_calc_fratio()
2237 Fref, refdiv, div, ratio); in arizona_calc_fratio()
[all …]
H A Dmadera.c3509 int refdiv, div; in madera_calc_fratio() local
3513 cfg->refdiv = 0; in madera_calc_fratio()
3517 cfg->refdiv++; in madera_calc_fratio()
3558 refdiv = cfg->refdiv; in madera_calc_fratio()
3567 cfg->refdiv = refdiv; in madera_calc_fratio()
3583 cfg->refdiv = refdiv; in madera_calc_fratio()
3591 refdiv++; in madera_calc_fratio()
3639 fref = fref / (1 << cfg->refdiv); in madera_calc_fll()
3708 cfg->fratio, ratio, cfg->refdiv, 1 << cfg->refdiv); in madera_calc_fll()
3741 cfg->refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT | in madera_write_fll()
[all …]
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c87 unsigned long refdiv; in clk_pll_recalc_rate() local
93 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; in clk_pll_recalc_rate()
96 do_div(vco_freq, refdiv); in clk_pll_recalc_rate()
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock() local
71 return (((FREF * pfdr) / refdiv) / busdiv); in get_sys_clock()
/openbmc/linux/drivers/clk/
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
58 refdiv = ((control >> 16) & 0x1f) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S14 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
16 ((0x1F & refdiv) << 16) | \
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S19 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
21 ((0x1F & refdiv) << 16) | \
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h61 u32 refdiv; member

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