| /openbmc/qemu/tests/tcg/loongarch64/ |
| H A D | test_pcadd.c | 9 uint64_t rd2 = 0; \
14 : "=r"(rd1), "=r"(rd2) \
16 rm = rd2 - rd1; \
|
| /openbmc/linux/arch/arm64/kernel/ |
| H A D | compat_alignment.c | 71 unsigned int rd2; in do_alignment_ldrdstrd() local
76 rd2 = (instr >> 8) & 0xf; in do_alignment_ldrdstrd()
82 rd2 = rd + 1; in do_alignment_ldrdstrd()
92 regs->regs[rd2] = val2; in do_alignment_ldrdstrd()
95 put_user(regs->regs[rd2], (u32 __user *)(addr + 4))) in do_alignment_ldrdstrd()
|
| /openbmc/linux/Documentation/translations/zh_CN/scheduler/ |
| H A D | sched-energy.rst | 92 RDs: |----rd1----|-----rd2-----|
95 每个根域包含6个CPU。这两个根域在上图中被表示为rd1和rd2。由于pd4与rd1和rd2
99 * rd2->pd: pd4 -> pd8
|
| /openbmc/linux/arch/arm/mm/ |
| H A D | alignment.c | 392 unsigned int rd2; in do_alignment_ldrdstrd() local
397 rd2 = (instr >> 8) & 0xf; in do_alignment_ldrdstrd()
403 rd2 = rd + 1; in do_alignment_ldrdstrd()
416 regs->uregs[rd2] = val; in do_alignment_ldrdstrd()
419 put32_unaligned_check(regs->uregs[rd2], addr + 4); in do_alignment_ldrdstrd()
435 regs->uregs[rd2] = val2; in do_alignment_ldrdstrd()
439 put32t_unaligned_check(regs->uregs[rd2], addr + 4); in do_alignment_ldrdstrd()
|
| /openbmc/qemu/target/riscv/ |
| H A D | xthead.decode | 17 %rd2 20:5
30 &th_pair rd1 rs rd2 sh2
42 @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
|
| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_bbt.c | 842 struct nand_bbt_descr *rd, *rd2; in check_create() local
854 rd2 = NULL; in check_create()
872 rd2 = md; in check_create()
915 if (rd2) { in check_create()
916 res2 = read_abs_bbt(mtd, buf, rd2, chipsel); in check_create()
919 rd2->pages[i] = -1; in check_create()
920 rd2->version[i] = 0; in check_create()
|
| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_bbt.c | 956 struct nand_bbt_descr *rd, *rd2; in check_create() local
968 rd2 = NULL; in check_create()
986 rd2 = md; in check_create()
1029 if (rd2) { in check_create()
1030 res2 = read_abs_bbt(this, buf, rd2, chipsel); in check_create()
1033 rd2->pages[i] = -1; in check_create()
1034 rd2->version[i] = 0; in check_create()
|
| /openbmc/qemu/target/rx/ |
| H A D | insns.decode | 460 # POP rd-rd2
461 POPM 0110 1111 rd:4 rd2:4
518 # RTSD #imm, rd-rd2
519 RTSD_irr 0011 1111 rd:4 rd2:4 imm:8
|
| H A D | translate.c | 631 if (a->rd == 0 || a->rd >= a->rd2) { in trans_POPM()
633 "Invalid register ranges r%d-r%d", a->rd, a->rd2); in trans_POPM()
636 while (r <= a->rd2 && r < 16) { in trans_POPM()
786 if (a->rd2 >= a->rd) { in trans_RTSD_irr()
787 adj = a->imm - (a->rd2 - a->rd + 1); in trans_RTSD_irr()
794 while (dst <= a->rd2 && dst < 16) { in trans_RTSD_irr()
|
| H A D | disas.c | 363 prt("popm\tr%d-r%d", a->rd, a->rd2); in trans_POPM()
435 prt("rtsd\t#%d, r%d - r%d", a->imm << 2, a->rd, a->rd2); in trans_RTSD_irr()
|
| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_its.c | 852 uint64_t rd1, rd2; in process_movall() local
855 rd2 = FIELD_EX64(cmdpkt[3], MOVALL_3, RDBASE2); in process_movall()
857 trace_gicv3_its_cmd_movall(rd1, rd2); in process_movall()
866 if (rd2 >= s->gicv3->num_cpu) { in process_movall()
870 __func__, rd2, s->gicv3->num_cpu); in process_movall()
874 if (rd1 == rd2) { in process_movall()
880 gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); in process_movall()
|
| H A D | trace-events | 206 gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " R…
|
| /openbmc/linux/net/wireless/ |
| H A D | reg.c | 1335 const struct ieee80211_regdomain *rd2, in reg_rules_intersect() argument
1371 max_bandwidth2 = reg_get_max_bandwidth(rd2, rule2); in reg_rules_intersect()
1498 const struct ieee80211_regdomain *rd2) in regdom_intersect() argument
1507 if (!rd1 || !rd2) in regdom_intersect()
1520 for (y = 0; y < rd2->n_reg_rules; y++) { in regdom_intersect()
1521 rule2 = &rd2->reg_rules[y]; in regdom_intersect()
1522 if (!reg_rules_intersect(rd1, rd2, rule1, rule2, in regdom_intersect()
1537 for (y = 0; y < rd2->n_reg_rules; y++) { in regdom_intersect()
1538 rule2 = &rd2->reg_rules[y]; in regdom_intersect()
1539 r = reg_rules_intersect(rd1, rd2, rule1, rule2, in regdom_intersect()
[all …]
|
| /openbmc/u-boot/drivers/net/ |
| H A D | sh_eth.c | 291 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf); in sh_eth_rx_desc_init()
545 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); in sh_eth_recv_common()
696 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); in sh_ether_recv()
|
| H A D | sh_eth.h | 77 u32 rd2; /* Buffer start */ member
|
| /openbmc/linux/Documentation/scheduler/ |
| H A D | sched-energy.rst | 104 RDs: |----rd1----|-----rd2-----|
108 containing 6 CPUs. The two root domains are denoted rd1 and rd2 in the
109 above figure. Since pd4 intersects with both rd1 and rd2, it will be
113 * rd2->pd: pd4 -> pd8
|
| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_xthead.c.inc | 910 if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
926 gen_set_gpr(ctx, a->rd2, t2);
953 TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
|
| /openbmc/qemu/target/mips/tcg/ |
| H A D | nanomips_translate.c.inc | 4790 int rd2 = extract32(ctx->opcode, 3, 1) << 1 |
4792 int r1 = gpr2reg1[rd2];
4793 int r2 = gpr2reg2[rd2];
|
| /openbmc/linux/Documentation/admin-guide/ |
| H A D | md.rst | 604 So for a 3 drive array there will be rd0, rd1, rd2.
|
| /openbmc/qemu/disas/ |
| H A D | nanomips.c | 10045 const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info); in MOVEP() local
10051 return img_format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4); in MOVEP()
10074 const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info); in MOVEP_REV_() local
10078 return img_format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2); in MOVEP_REV_()
|