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Searched refs:qts (Results 1 – 25 of 149) sorted by relevance

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/openbmc/qemu/tests/qtest/
H A Dvirtio-net-failover.c42 QTestState *qts; in machine_start() local
46 qts = qtest_init(args); in machine_start()
48 pc_alloc_init(&guest_malloc, qts, 0); in machine_start()
49 pcibus = qpci_new_pc(qts, &guest_malloc); in machine_start()
62 return qts; in machine_start()
65 static void machine_stop(QTestState *qts) in machine_stop() argument
69 qtest_quit(qts); in machine_stop()
74 QTestState *qts; in test_error_id() local
78 qts = machine_start(BASE_MACHINE in test_error_id()
82 resp = qtest_qmp(qts, "{'execute': 'device_add'," in test_error_id()
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H A Dmicrobit-test.c28 static bool uart_wait_for_event(QTestState *qts, uint32_t event_addr) in uart_wait_for_event() argument
33 if (qtest_readl(qts, event_addr) == 1) { in uart_wait_for_event()
34 qtest_writel(qts, event_addr, 0x00); in uart_wait_for_event()
49 static void uart_rw_to_rxd(QTestState *qts, int sock_fd, const char *in, in uart_rw_to_rxd() argument
56 g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + in uart_rw_to_rxd()
58 out[i] = qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD); in uart_rw_to_rxd()
63 static void uart_w_to_txd(QTestState *qts, const char *in) in uart_w_to_txd() argument
68 qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, in[i]); in uart_w_to_txd()
69 g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + in uart_w_to_txd()
78 QTestState *qts = qtest_init_with_serial("-M microbit", &sock_fd); in test_nrf51_uart() local
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H A Dendianness-test.c50 static uint8_t isa_inb(QTestState *qts, const TestCase *test, uint16_t addr) in isa_inb() argument
54 value = qtest_inb(qts, addr); in isa_inb()
56 value = qtest_readb(qts, test->isa_base + addr); in isa_inb()
61 static uint16_t isa_inw(QTestState *qts, const TestCase *test, uint16_t addr) in isa_inw() argument
65 value = qtest_inw(qts, addr); in isa_inw()
67 value = qtest_readw(qts, test->isa_base + addr); in isa_inw()
72 static uint32_t isa_inl(QTestState *qts, const TestCase *test, uint16_t addr) in isa_inl() argument
76 value = qtest_inl(qts, addr); in isa_inl()
78 value = qtest_readl(qts, test->isa_base + addr); in isa_inl()
83 static void isa_outb(QTestState *qts, const TestCase *test, uint16_t addr, in isa_outb() argument
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H A Ddrive_del-test.c21 static bool look_for_drive0(QTestState *qts, const char *command, const char *key) in look_for_drive0() argument
28 response = qtest_qmp(qts, "{'execute': %s}", command); in look_for_drive0()
58 static bool has_drive(QTestState *qts) in has_drive() argument
60 return look_for_drive0(qts, "query-block", "device"); in has_drive()
63 static bool has_blockdev(QTestState *qts) in has_blockdev() argument
65 return look_for_drive0(qts, "query-named-block-nodes", "node-name"); in has_blockdev()
68 static void blockdev_add_with_media(QTestState *qts) in blockdev_add_with_media() argument
72 response = qtest_qmp(qts, in blockdev_add_with_media()
87 g_assert(has_blockdev(qts)); in blockdev_add_with_media()
90 static void drive_add(QTestState *qts) in drive_add() argument
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H A Ddm163-test.c24 #define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \
33 static void rise_gpio_pin_dck(QTestState *qts) in rise_gpio_pin_dck() argument
36 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in rise_gpio_pin_dck()
38 qtest_writel(qts, 0x48000414, 0x00000002); in rise_gpio_pin_dck()
41 static void lower_gpio_pin_dck(QTestState *qts) in lower_gpio_pin_dck() argument
44 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in lower_gpio_pin_dck()
46 qtest_writel(qts, 0x48000414, 0x00000000); in lower_gpio_pin_dck()
49 static void rise_gpio_pin_selbk(QTestState *qts) in rise_gpio_pin_selbk() argument
52 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in rise_gpio_pin_selbk()
54 qtest_writel(qts, 0x48000814, 0x00000020); in rise_gpio_pin_selbk()
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H A Darm-cpu-features.c29 static QDict *do_query_no_props(QTestState *qts, const char *cpu_type) in do_query_no_props() argument
31 return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }" in do_query_no_props()
36 static QDict *do_query(QTestState *qts, const char *cpu_type, in do_query() argument
49 resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, " in do_query()
53 resp = do_query_no_props(qts, cpu_type); in do_query()
73 #define assert_error(qts, cpu_type, expected_error, fmt, ...) \ argument
78 _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__); \
130 #define assert_has_feature(qts, cpu_type, feature) \ argument
132 QDict *_resp = do_query_no_props(qts, cpu_type); \
139 #define assert_has_not_feature(qts, cpu_type, feature) \ argument
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H A Dnpcm7xx_smbus-test.c161 static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) in choose_bank() argument
163 uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3); in choose_bank()
171 qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); in choose_bank()
174 static void check_running(QTestState *qts, uint64_t base_addr) in check_running() argument
176 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_running()
177 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_running()
180 static void check_stopped(QTestState *qts, uint64_t base_addr) in check_stopped() argument
184 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); in check_stopped()
185 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_stopped()
186 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_stopped()
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H A Dnpcm7xx_watchdog_timer-test.c65 static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd) in watchdog_read_wtcr() argument
67 return qtest_readl(qts, wd->base_addr + WTCR_OFFSET); in watchdog_read_wtcr()
70 static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd, in watchdog_write_wtcr() argument
73 qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value); in watchdog_write_wtcr()
76 static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd) in watchdog_prescaler() argument
78 switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) { in watchdog_prescaler()
92 static QDict *get_watchdog_action(QTestState *qts) in get_watchdog_action() argument
94 QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG"); in get_watchdog_action()
104 static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd) in watchdog_interrupt_cycles() argument
106 uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2); in watchdog_interrupt_cycles()
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H A Dstm32l4x5_usart-test.c53 static bool check_nvic_pending(QTestState *qts, unsigned int n) in check_nvic_pending() argument
58 return qtest_readl(qts, NVIC_ISPR1) & (1 << n); in check_nvic_pending()
61 static bool clear_nvic_pending(QTestState *qts, unsigned int n) in clear_nvic_pending() argument
66 qtest_writel(qts, NVIC_ICPR1, (1 << n)); in clear_nvic_pending()
75 static bool usart_wait_for_flag(QTestState *qts, uint32_t event_addr, in usart_wait_for_flag() argument
79 if ((qtest_readl(qts, event_addr) & flag)) { in usart_wait_for_flag()
88 static void usart_receive_string(QTestState *qts, int sock_fd, const char *in, in usart_receive_string() argument
95 g_assert_true(usart_wait_for_flag(qts, in usart_receive_string()
97 out[i] = qtest_readl(qts, USART1_BASE_ADDR + A_RDR); in usart_receive_string()
102 static void usart_send_string(QTestState *qts, const char *in) in usart_send_string() argument
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H A Dsifive-e-aon-watchdog-test.c49 static void test_init(QTestState *qts) in test_init() argument
51 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
52 qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); in test_init()
54 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
55 qtest_writel(qts, WDOG_BASE + WDOGCFG, 0); in test_init()
57 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
58 qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF); in test_init()
64 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogcount() local
66 test_init(qts); in test_wdogcount()
68 tmp = qtest_readl(qts, WDOG_BASE + WDOGCOUNT); in test_wdogcount()
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H A Dxlnx-can-test.c89 static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) in read_data() argument
94 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; in read_data()
99 buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET); in read_data()
100 buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); in read_data()
101 buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); in read_data()
102 buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); in read_data()
105 qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); in read_data()
108 static void send_data(QTestState *qts, uint64_t can_base_addr, in send_data() argument
114 qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); in send_data()
115 qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); in send_data()
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H A Dpnv-xive2-test.c21 static void set_table(QTestState *qts, uint64_t type, uint64_t addr) in set_table() argument
55 pnv_xive_xscom_write(qts, X_VC_VSD_TABLE_ADDR, type << 48); in set_table()
56 pnv_xive_xscom_write(qts, X_VC_VSD_TABLE_DATA, vsd); in set_table()
59 pnv_xive_xscom_write(qts, X_PC_VSD_TABLE_ADDR, type << 48); in set_table()
60 pnv_xive_xscom_write(qts, X_PC_VSD_TABLE_DATA, vsd); in set_table()
64 static void set_tima8(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima8() argument
70 qtest_writeb(qts, ic_addr + offset, b); in set_tima8()
73 static void set_tima32(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima32() argument
79 qtest_writel(qts, ic_addr + offset, l); in set_tima32()
82 static uint8_t get_tima8(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima8() argument
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H A Dqmp-test.c36 static void assert_recovered(QTestState *qts) in assert_recovered() argument
40 resp = qtest_qmp(qts, "{ 'execute': 'no-such-cmd' }"); in assert_recovered()
44 static void test_malformed(QTestState *qts) in test_malformed() argument
49 qtest_qmp_send_raw(qts, "{]\n"); in test_malformed()
50 resp = qtest_qmp_receive_dict(qts); in test_malformed()
52 assert_recovered(qts); in test_malformed()
55 qtest_qmp_send_raw(qts, "{\xFF"); in test_malformed()
56 resp = qtest_qmp_receive_dict(qts); in test_malformed()
58 assert_recovered(qts); in test_malformed()
61 qtest_qmp_send_raw(qts, "{\x01"); in test_malformed()
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H A Dnpcm7xx_pwm-test.c221 static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name) in pwm_qom_get() argument
229 response = qtest_qmp(qts, "{ 'execute': 'qom-get'," in pwm_qom_get()
239 static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index) in pwm_get_freq() argument
247 return pwm_qom_get(qts, path, name); in pwm_get_freq()
250 static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index) in pwm_get_duty() argument
258 return pwm_qom_get(qts, path, name); in pwm_get_duty()
261 static void mft_qom_set(QTestState *qts, int index, const char *name, in mft_qom_set() argument
271 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in mft_qom_set()
288 static uint64_t read_pclk(QTestState *qts, bool mft) in read_pclk() argument
291 uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); in read_pclk()
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H A Dxlnx-canfd-test.c90 static void enable_filters(QTestState *qts) in enable_filters() argument
119 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
121 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
125 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
127 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
132 qtest_writel(qts, CANFD0_BASE_ADDR + R_FILTER_CONTROL_REGISTER, in enable_filters()
134 qtest_writel(qts, CANFD1_BASE_ADDR + R_FILTER_CONTROL_REGISTER, in enable_filters()
138 static void configure_canfd(QTestState *qts, uint8_t mode) in configure_canfd() argument
143 qtest_writel(qts, CANFD0_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE); in configure_canfd()
144 qtest_writel(qts, CANFD1_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE); in configure_canfd()
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H A Dnpcm7xx_adc-test.c98 static uint32_t adc_read_con(QTestState *qts, const ADC *adc) in adc_read_con() argument
100 return qtest_readl(qts, adc->base_addr + CON_OFFSET); in adc_read_con()
103 static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) in adc_write_con() argument
105 qtest_writel(qts, adc->base_addr + CON_OFFSET, value); in adc_write_con()
108 static uint32_t adc_read_data(QTestState *qts, const ADC *adc) in adc_read_data() argument
110 return qtest_readl(qts, adc->base_addr + DATA_OFFSET); in adc_read_data()
119 static void adc_qom_set(QTestState *qts, const ADC *adc, in adc_qom_set() argument
127 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in adc_qom_set()
135 static void adc_write_input(QTestState *qts, const ADC *adc, in adc_write_input() argument
141 adc_qom_set(qts, adc, name, value); in adc_write_input()
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H A Dvirtio-iommu-test.c59 static int send_attach_detach(QTestState *qts, QVirtioIOMMU *v_iommu, in send_attach_detach() argument
79 qtest_memwrite(qts, ro_addr, &req, ro_size); in send_attach_detach()
80 free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); in send_attach_detach()
81 qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); in send_attach_detach()
82 qvirtqueue_kick(qts, dev, vq, free_head); in send_attach_detach()
83 qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, in send_attach_detach()
85 qtest_memread(qts, wr_addr, &buffer, wr_size); in send_attach_detach()
100 static int send_map(QTestState *qts, QVirtioIOMMU *v_iommu, in send_map() argument
124 qtest_memwrite(qts, ro_addr, &req, ro_size); in send_map()
125 free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); in send_map()
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H A Ddevice-introspect-test.c28 static QList *qom_list_types(QTestState * qts, const char *implements, in qom_list_types() argument
39 resp = qtest_qmp(qts, "{'execute': 'qom-list-types', 'arguments': %p }", in qom_list_types()
98 static QList *device_type_list(QTestState *qts, bool abstract) in device_type_list() argument
100 return qom_list_types(qts, "device", abstract); in device_type_list()
103 static void test_one_device(QTestState *qts, const char *type) in test_one_device() argument
111 resp = qtest_qmp(qts, "{'execute': 'device-list-properties'," in test_one_device()
120 help = qtest_hmp(qts, "device_add \"%s,help\"", escaped); in test_one_device()
129 QTestState *qts; in test_device_intro_list() local
131 qts = qtest_init(common_args); in test_device_intro_list()
133 types = device_type_list(qts, true); in test_device_intro_list()
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H A Dpnv-xive2-flush-sync.c57 static uint8_t get_sync(QTestState *qts, uint32_t src_pir, int ic_topo_id, in get_sync() argument
61 return qtest_readb(qts, addr); in get_sync()
64 static void clr_sync(QTestState *qts, uint32_t src_pir, int ic_topo_id, in clr_sync() argument
68 qtest_writeb(qts, addr, 0x0); in clr_sync()
71 static void inject_cache_flush(QTestState *qts, int ic_topo_id, in inject_cache_flush() argument
75 pnv_xive_xscom_write(qts, scom_addr, 0); in inject_cache_flush()
78 static void inject_queue_sync(QTestState *qts, int ic_topo_id, uint64_t offset) in inject_queue_sync() argument
82 qtest_writeq(qts, addr, 0); in inject_queue_sync()
85 static void inject_op(QTestState *qts, int ic_topo_id, int type) in inject_op() argument
89 inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_IPI); in inject_op()
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H A Dnpcm7xx_emc-test.c242 static uint32_t emc_read(QTestState *qts, const EMCModule *mod, in emc_read() argument
245 return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); in emc_read()
249 static void emc_write(QTestState *qts, const EMCModule *mod, in emc_write() argument
252 qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); in emc_write()
255 static void emc_read_tx_desc(QTestState *qts, uint32_t addr, in emc_read_tx_desc() argument
258 qtest_memread(qts, addr, desc, sizeof(*desc)); in emc_read_tx_desc()
265 static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc, in emc_write_tx_desc() argument
274 qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); in emc_write_tx_desc()
277 static void emc_read_rx_desc(QTestState *qts, uint32_t addr, in emc_read_rx_desc() argument
280 qtest_memread(qts, addr, desc, sizeof(*desc)); in emc_read_rx_desc()
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H A Dnpcm7xx_sdhci-test.c35 QTestState *qts = qtest_initf( in setup_sd_card() local
41 qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL); in setup_sd_card()
42 qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON, in setup_sd_card()
45 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD); in setup_sd_card()
46 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8)); in setup_sd_card()
47 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID); in setup_sd_card()
48 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR in setup_sd_card()
50 rca = qtest_readl(qts, NPCM7XX_MMC_BA + SDHC_RSPREG0) >> 16; in setup_sd_card()
51 sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, rca << 16, 0, in setup_sd_card()
54 return qts; in setup_sd_card()
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H A Dpnv-spi-seeprom-test.c37 static void pnv_spi_xscom_write(QTestState *qts, const PnvChip *chip, in pnv_spi_xscom_write() argument
41 qtest_writeq(qts, pnv_xscom_addr(chip, pcba), val); in pnv_spi_xscom_write()
44 static uint64_t pnv_spi_xscom_read(QTestState *qts, const PnvChip *chip, in pnv_spi_xscom_read() argument
48 return qtest_readq(qts, pnv_xscom_addr(chip, pcba)); in pnv_spi_xscom_read()
51 static void spi_seeprom_transaction(QTestState *qts, const PnvChip *chip) in spi_seeprom_transaction() argument
54 pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, READ_OP_COUNTER_CONFIG); in spi_seeprom_transaction()
55 pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, READ_OP_SEQUENCER); in spi_seeprom_transaction()
56 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, READ_OP_TDR_DATA); in spi_seeprom_transaction()
57 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, 0); in spi_seeprom_transaction()
59 uint64_t rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG); in spi_seeprom_transaction()
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H A Dide-test.c131 QTestState *qts; in ide_test_start() local
136 qts = qtest_vinitf(full_fmt, ap); in ide_test_start()
139 pc_alloc_init(&guest_malloc, qts, 0); in ide_test_start()
141 return qts; in ide_test_start()
144 static void ide_test_quit(QTestState *qts) in ide_test_quit() argument
151 qtest_quit(qts); in ide_test_quit()
154 static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar *bmdma_bar, in get_pci_device() argument
161 pcibus = qpci_new_pc(qts, NULL); in get_pci_device()
203 static int send_dma_request(QTestState *qts, int cmd, uint64_t sector, in send_dma_request() argument
216 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); in send_dma_request()
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H A Dvhost-user-blk-test.c70 QTestState *qts = global_qtest; in virtio_blk_request() local
90 qtest_memwrite(qts, addr, req, 16); in virtio_blk_request()
91 qtest_memwrite(qts, addr + 16, req->data, data_size); in virtio_blk_request()
92 qtest_memwrite(qts, addr + 16 + data_size, &status, sizeof(status)); in virtio_blk_request()
99 QTestState *qts, in test_invalid_discard_write_zeroes() argument
125 free_head = qvirtqueue_add(qts, vq, req_addr, 16, false, true); in test_invalid_discard_write_zeroes()
126 qvirtqueue_add(qts, vq, req_addr + 16, sizeof(dwz_hdr2), false, true); in test_invalid_discard_write_zeroes()
127 qvirtqueue_add(qts, vq, req_addr + 16 + sizeof(dwz_hdr2), 1, true, in test_invalid_discard_write_zeroes()
130 qvirtqueue_kick(qts, dev, vq, free_head); in test_invalid_discard_write_zeroes()
132 qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, in test_invalid_discard_write_zeroes()
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Dpci-pc.c26 return qtest_inb(bus->qts, addr); in qpci_pc_pio_readb()
31 qtest_outb(bus->qts, addr, val); in qpci_pc_pio_writeb()
36 return qtest_inw(bus->qts, addr); in qpci_pc_pio_readw()
41 qtest_outw(bus->qts, addr, val); in qpci_pc_pio_writew()
46 return qtest_inl(bus->qts, addr); in qpci_pc_pio_readl()
51 qtest_outl(bus->qts, addr, val); in qpci_pc_pio_writel()
56 return (uint64_t)qtest_inl(bus->qts, addr) + in qpci_pc_pio_readq()
57 ((uint64_t)qtest_inl(bus->qts, addr + 4) << 32); in qpci_pc_pio_readq()
62 qtest_outl(bus->qts, addr, val & 0xffffffff); in qpci_pc_pio_writeq()
63 qtest_outl(bus->qts, addr + 4, val >> 32); in qpci_pc_pio_writeq()
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