Home
last modified time | relevance | path

Searched refs:qtest_readl (Results 1 – 25 of 39) sorted by relevance

12

/openbmc/qemu/tests/qtest/
H A Dsifive-e-aon-watchdog-test.c68 tmp = qtest_readl(qts, WDOG_BASE + WDOGCOUNT); in test_wdogcount()
70 g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == tmp); in test_wdogcount()
74 g_assert(0xBEEF == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); in test_wdogcount()
78 g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); in test_wdogcount()
82 g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); in test_wdogcount()
86 g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT)); in test_wdogcount()
98 tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_wdogcfg()
100 g_assert(qtest_readl(qts, WDOG_BASE + WDOGCFG) == tmp_cfg); in test_wdogcfg()
104 g_assert(0xFFFFFFFF == qtest_readl(qts, WDOG_BASE + WDOGCFG)); in test_wdogcfg()
106 tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_wdogcfg()
[all …]
H A Dmicrobit-test.c33 if (qtest_readl(qts, event_addr) == 1) { in uart_wait_for_event()
58 out[i] = qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD); in uart_rw_to_rxd()
81 g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), ==, 0x00); in test_nrf51_uart()
88 g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), ==, 'c'); in test_nrf51_uart()
91 g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), ==, 0x04); in test_nrf51_uart()
93 g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), ==, 0x00); in test_nrf51_uart()
123 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); in i2c_read_byte()
128 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); in i2c_read_byte()
130 val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_REG_RXD); in i2c_read_byte()
174 g_assert_cmphex(qtest_readl(qts, base + i * 4), ==, 0xFFFFFFFF); in fill_and_erase()
[all …]
H A Daspeed_hace-test.c170 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_md5()
178 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); in test_md5()
182 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_md5()
203 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256()
211 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); in test_sha256()
215 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256()
236 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512()
244 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); in test_sha512()
248 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha512()
280 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); in test_sha256_sg()
[all …]
H A Dxlnx-can-test.c94 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; in read_data()
99 buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET); in read_data()
100 buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); in read_data()
101 buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); in read_data()
102 buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); in read_data()
120 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; in send_data()
153 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_bus()
156 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_bus()
189 status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); in test_can_loopback()
203 status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); in test_can_loopback()
[all …]
H A Dstm32l4x5_usart-test.c58 return qtest_readl(qts, NVIC_ISPR1) & (1 << n); in check_nvic_pending()
79 if ((qtest_readl(qts, event_addr) & flag)) { in usart_wait_for_flag()
97 out[i] = qtest_readl(qts, USART1_BASE_ADDR + A_RDR); in usart_receive_string()
138 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CR)); in init_clocks()
148 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR)); in init_clocks()
191 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in init_uart()
206 const uint32_t tdr = qtest_readl(qts, USART1_BASE_ADDR + A_TDR); in test_write_read()
223 g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'a'); in test_receive_char()
227 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in test_receive_char()
232 g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'b'); in test_receive_char()
[all …]
H A Dxlnx-canfd-test.c153 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in configure_canfd()
157 status = qtest_readl(qts, CANFD1_BASE_ADDR + R_SR_OFFSET); in configure_canfd()
192 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; in read_data()
197 fifo_status_reg_value = qtest_readl(qts, can_base_addr + in read_data()
207 buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET); in read_data()
208 buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET); in read_data()
211 buf_rx[i + 2] = qtest_readl(qts, in read_data()
245 int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; in send_data()
299 status = qtest_readl(qts, CANFD0_BASE_ADDR + R_SR_OFFSET); in test_can_data_transfer()
303 status = qtest_readl(qts, CANFD1_BASE_ADDR + R_SR_OFFSET); in test_can_data_transfer()
[all …]
H A Dast2700-gpio-test.c30 value = qtest_readl(s, offset); in test_output_pins()
35 value = qtest_readl(s, offset); in test_output_pins()
61 value = qtest_readl(s, offset); in test_input_pins()
66 value = qtest_readl(s, offset); in test_input_pins()
H A Daspeed_gpio-test.c67 value = qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); in test_set_input_pins()
71 value = qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); in test_set_input_pins()
H A Dtpm-util.c38 start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); in tpm_util_crb_transfer()
46 start = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START); in tpm_util_crb_transfer()
48 sts = qtest_readl(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_STS); in tpm_util_crb_transfer()
H A Dqtest_aspeed.c27 v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN; in aspeed_i2c_startup()
54 v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8; in aspeed_i2c_read_n()
H A Dnpcm7xx_pwm-test.c291 uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); in read_pclk()
293 uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); in read_pclk()
294 uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); in read_pclk()
299 pllcon = qtest_readl(qts, CLK_BA + PLLCON0); in read_pclk()
303 pllcon = qtest_readl(qts, CLK_BA + PLLCON1); in read_pclk()
365 return qtest_readl(qts, td->module->base_addr + offset); in pwm_read()
H A Dfuzz-xlnx-dp-test.c18 qtest_readl(s, 0xfd4a03ac); in test_fuzz_xlnx_dp_0x3ac()
H A Dnpcm7xx_sdhci-test.c50 rca = qtest_readl(qts, NPCM7XX_MMC_BA + SDHC_RSPREG0) >> 16; in setup_sd_card()
143 g_assert_cmphex(qtest_readl(qts, addr) | mask, ==, in test_reset()
H A Dtpm-tis-util.c465 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer()
479 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer()
485 sts = qtest_readl(s, TIS_REG(0, TPM_TIS_REG_STS)); in tpm_tis_transfer()
H A Dprom-env-test.c36 signature = qtest_readl(qts, ADDRESS); in check_guest_memory()
H A Dpnv-xive2-test.c103 return qtest_readl(qts, ic_addr + offset); in get_tima32()
250 reg32 = qtest_readl(qts, xive_get_queue_addr(end_index)); in test_hw_irq()
H A Dlibqtest-single.h252 return qtest_readl(global_qtest, addr); in readl()
H A Dnpcm7xx_adc-test.c100 return qtest_readl(qts, adc->base_addr + CON_OFFSET); in adc_read_con()
110 return qtest_readl(qts, adc->base_addr + DATA_OFFSET); in adc_read_data()
H A Daspeed_fsi-test.c46 return qtest_readl(s, aspeed_fsi_base_addr + reg); in aspeed_fsi_readl()
H A Dnpcm_gmac-test.c174 return qtest_readl(qts, mod->base_addr + regno); in gmac_read()
/openbmc/qemu/tests/qtest/libqos/
H A Dvirtio-mmio.c34 return qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off); in qvirtio_mmio_config_readl()
50 lo = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES); in qvirtio_mmio_get_features()
54 hi = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES); in qvirtio_mmio_get_features()
83 return (uint8_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS); in qvirtio_mmio_get_status()
97 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1; in qvirtio_mmio_get_queue_isr_status()
111 isr = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2; in qvirtio_mmio_get_config_isr_status()
137 g_assert_cmphex(qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN), ==, 0); in qvirtio_mmio_queue_select()
143 return (uint16_t)qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM_MAX); in qvirtio_mmio_get_queue_size()
242 magic = qtest_readl(qts, addr + QVIRTIO_MMIO_MAGIC_VALUE); in qvirtio_mmio_init_device()
245 dev->version = qtest_readl(qts, addr + QVIRTIO_MMIO_VERSION); in qvirtio_mmio_init_device()
[all …]
H A Dsdhci-cmd.c32 msg_frag = qtest_readl(qts, reg); in read_fifo()
H A Drtas.c26 ret[i] = qtest_readl(qts, target_ret + i * sizeof(uint32_t)); in qrtas_copy_ret()
H A Dvirtio-pci.c134 data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr); in qvirtio_pci_get_queue_isr_status()
158 data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr); in qvirtio_pci_get_config_isr_status()
/openbmc/qemu/tests/qtest/fuzz/
H A Dmeson.build25 '-Wl,-wrap,qtest_readl',

12